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| author | Luke Geeson <luke.geeson@arm.com> | 2018-06-04 09:41:32 +0000 |
|---|---|---|
| committer | Luke Geeson <luke.geeson@arm.com> | 2018-06-04 09:41:32 +0000 |
| commit | 43e4367961958fa973677f3464f796371f04070b (patch) | |
| tree | f104bdffc671b5cd1e20fa93d868f78d84ba30ce /llvm/lib/Target/AArch64 | |
| parent | 3ca31ba75a405899bcc3e6a67abd9e9eee0f8666 (diff) | |
| download | bcm5719-llvm-43e4367961958fa973677f3464f796371f04070b.tar.gz bcm5719-llvm-43e4367961958fa973677f3464f796371f04070b.zip | |
[AArch64] Audit on rL333634 to fix FP16 Disasm BitPatterns
llvm-svn: 333879
Diffstat (limited to 'llvm/lib/Target/AArch64')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrFormats.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.td | 1 |
2 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 861cdc8109c..69a5f849833 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -7928,9 +7928,10 @@ multiclass SIMDFPScalarRShift<bit U, bits<5> opc, string asm> { let Inst{19-16} = imm{3-0}; let Inst{23-22} = 0b11; } - def SHr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?}, + def SHr : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?}, FPR32, FPR16, vecshiftR32, asm, []> { let Inst{19-16} = imm{3-0}; + let Inst{22-21} = 0b01; } def HDr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?}, FPR16, FPR64, vecshiftR32, asm, []> { diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index ac7bc9873c5..b9d88fc87b3 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -4984,7 +4984,6 @@ def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn), def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm), (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>; - defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>; defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">; defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn", |
