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| author | Sander de Smalen <sander.desmalen@arm.com> | 2018-07-17 09:48:57 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2018-07-17 09:48:57 +0000 |
| commit | 3b9e342ae14fd4a041769280640c78e4bb597b06 (patch) | |
| tree | d34c43ef3faf9d7079ffb303f78444ffb89ef7d7 /llvm/lib/Target/AArch64 | |
| parent | e4d12bb2d61eb5d7401d6cab2f990e43d1081f2c (diff) | |
| download | bcm5719-llvm-3b9e342ae14fd4a041769280640c78e4bb597b06.tar.gz bcm5719-llvm-3b9e342ae14fd4a041769280640c78e4bb597b06.zip | |
[AArch64][SVE] Asm: Support for predicated FP operations.
This patch adds support for the following floating point
instructions:
FABD (absolute difference)
FADD (addition)
FSUB (subtract)
FSUBR (subtract reverse form)
FDIV (divide)
FDIVR (divide reverse form)
FMAX (maximum)
FMAXNM (maximum number)
FMIN (minimum)
FMINNM (minimum number)
FSCALE (adjust exponent)
FMULX (multiply extended)
All operations are predicated and binary form, e.g.
fadd z0.h, p0/m, z0.h, z1.h
^___________^ (tied)
Supporting 16, 32 and 64-bit FP elements.
llvm-svn: 337259
Diffstat (limited to 'llvm/lib/Target/AArch64')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 14 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 28 |
2 files changed, 42 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 1edc36944a1..521253baf63 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -85,6 +85,20 @@ let Predicates = [HasSVE] in { defm FMUL_ZPmI : sve_fp_2op_i_p_zds<0b010, "fmul", sve_fpimm_half_two>; defm FMAX_ZPmI : sve_fp_2op_i_p_zds<0b110, "fmax", sve_fpimm_zero_one>; + defm FADD_ZPmZ : sve_fp_2op_p_zds<0b0000, "fadd">; + defm FSUB_ZPmZ : sve_fp_2op_p_zds<0b0001, "fsub">; + defm FMUL_ZPmZ : sve_fp_2op_p_zds<0b0010, "fmul">; + defm FSUBR_ZPmZ : sve_fp_2op_p_zds<0b0011, "fsubr">; + defm FMAXNM_ZPmZ : sve_fp_2op_p_zds<0b0100, "fmaxnm">; + defm FMINNM_ZPmZ : sve_fp_2op_p_zds<0b0101, "fminnm">; + defm FMAX_ZPmZ : sve_fp_2op_p_zds<0b0110, "fmax">; + defm FMIN_ZPmZ : sve_fp_2op_p_zds<0b0111, "fmin">; + defm FABD_ZPmZ : sve_fp_2op_p_zds<0b1000, "fabd">; + defm FSCALE_ZPmZ : sve_fp_2op_p_zds<0b1001, "fscale">; + defm FMULX_ZPmZ : sve_fp_2op_p_zds<0b1010, "fmulx">; + defm FDIVR_ZPmZ : sve_fp_2op_p_zds<0b1100, "fdivr">; + defm FDIV_ZPmZ : sve_fp_2op_p_zds<0b1101, "fdiv">; + defm FCADD_ZPmZ : sve_fp_fcadd<"fcadd">; defm FCMLA_ZPmZZ : sve_fp_fcmla<"fcmla">; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 2c37be691bb..5be8ef1afd2 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -958,6 +958,34 @@ multiclass sve_fp_2op_i_p_zds<bits<3> opc, string asm, Operand imm_ty> { def _D : sve_fp_2op_i_p_zds<0b11, opc, asm, ZPR64, imm_ty>; } +class sve_fp_2op_p_zds<bits<2> sz, bits<4> opc, string asm, + ZPRRegOp zprty> +: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), + asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Zdn; + bits<5> Zm; + let Inst{31-24} = 0b01100101; + let Inst{23-22} = sz; + let Inst{21-20} = 0b00; + let Inst{19-16} = opc; + let Inst{15-13} = 0b100; + let Inst{12-10} = Pg; + let Inst{9-5} = Zm; + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; +} + +multiclass sve_fp_2op_p_zds<bits<4> opc, string asm> { + def _H : sve_fp_2op_p_zds<0b01, opc, asm, ZPR16>; + def _S : sve_fp_2op_p_zds<0b10, opc, asm, ZPR32>; + def _D : sve_fp_2op_p_zds<0b11, opc, asm, ZPR64>; +} + + //===----------------------------------------------------------------------===// // SVE Floating Point Multiply - Indexed Group //===----------------------------------------------------------------------===// |
