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| author | Danilo Carvalho Grael <danilo.carvalho.grael@huawei.com> | 2020-01-13 17:47:02 -0500 |
|---|---|---|
| committer | Danilo Carvalho Grael <danilo.carvalho.grael@huawei.com> | 2020-01-14 15:26:19 -0500 |
| commit | 26d96126a0d258afccfeec1fbaa727bfeb820308 (patch) | |
| tree | 3def53406f236b4902272e656802b0b726fc0295 /llvm/lib/Target/AArch64 | |
| parent | 5d1b3ba687690bbb37f911f66a2c2c5f19d60032 (diff) | |
| download | bcm5719-llvm-26d96126a0d258afccfeec1fbaa727bfeb820308.tar.gz bcm5719-llvm-26d96126a0d258afccfeec1fbaa727bfeb820308.zip | |
[SVE] Add patterns for MUL immediate instruction.
Summary: Add the missing MUL pattern for integer immediate instructions.
Reviewers: sdesmalen, huntergr, efriedma, c-rhodes, kmclaughlin
Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits, amehsan
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72654
Diffstat (limited to 'llvm/lib/Target/AArch64')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 7 |
2 files changed, 7 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 82af6dc0074..a4d0ac89e84 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -135,7 +135,7 @@ let Predicates = [HasSVE] in { defm UMAX_ZI : sve_int_arith_imm1_unsigned<0b01, "umax", umax>; defm UMIN_ZI : sve_int_arith_imm1_unsigned<0b11, "umin", umin>; - defm MUL_ZI : sve_int_arith_imm2<"mul">; + defm MUL_ZI : sve_int_arith_imm2<"mul", mul>; defm MUL_ZPmZ : sve_int_bin_pred_arit_2<0b000, "mul", int_aarch64_sve_mul>; defm SMULH_ZPmZ : sve_int_bin_pred_arit_2<0b010, "smulh", int_aarch64_sve_smulh>; defm UMULH_ZPmZ : sve_int_bin_pred_arit_2<0b011, "umulh", int_aarch64_sve_umulh>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 385d1267be2..a172b8d7e6b 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -3537,11 +3537,16 @@ multiclass sve_int_arith_imm1_unsigned<bits<2> opc, string asm, SDPatternOperato def : SVE_1_Op_Imm_Arith_Pat<nxv2i64, op, ZPR64, i64, SVEArithUImmPat, !cast<Instruction>(NAME # _D)>; } -multiclass sve_int_arith_imm2<string asm> { +multiclass sve_int_arith_imm2<string asm, SDPatternOperator op> { def _B : sve_int_arith_imm<0b00, 0b110000, asm, ZPR8, simm8>; def _H : sve_int_arith_imm<0b01, 0b110000, asm, ZPR16, simm8>; def _S : sve_int_arith_imm<0b10, 0b110000, asm, ZPR32, simm8>; def _D : sve_int_arith_imm<0b11, 0b110000, asm, ZPR64, simm8>; + + def : SVE_1_Op_Imm_Arith_Pat<nxv16i8, op, ZPR8, i32, SVEArithSImmPat, !cast<Instruction>(NAME # _B)>; + def : SVE_1_Op_Imm_Arith_Pat<nxv8i16, op, ZPR16, i32, SVEArithSImmPat, !cast<Instruction>(NAME # _H)>; + def : SVE_1_Op_Imm_Arith_Pat<nxv4i32, op, ZPR32, i32, SVEArithSImmPat, !cast<Instruction>(NAME # _S)>; + def : SVE_1_Op_Imm_Arith_Pat<nxv2i64, op, ZPR64, i64, SVEArithSImmPat, !cast<Instruction>(NAME # _D)>; } //===----------------------------------------------------------------------===// |
