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author | Ehsan Amiri <ehsanamiri@gmail.com> | 2019-10-29 12:08:00 -0400 |
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committer | amehsan <e00408328@ptlaby04.huawei.com> | 2019-10-29 13:17:30 -0400 |
commit | 1e9de0215f0488bae6c2a7cc0c9c4324d981ad30 (patch) | |
tree | 8b2cd5a919631bd23bba3af1315190a3215d74b5 /llvm/lib/Target/AArch64 | |
parent | 94bfa6deb0d6077af6694d8a3048fe7bb0910a12 (diff) | |
download | bcm5719-llvm-1e9de0215f0488bae6c2a7cc0c9c4324d981ad30.tar.gz bcm5719-llvm-1e9de0215f0488bae6c2a7cc0c9c4324d981ad30.zip |
[SVE][AArch64] Adding pattern matching for some SVE instructions.
Adding patten matching for two SVE intrinsics: frecps and frsqrts.
Also added patterns for fsub and fmul - these SDNodes directly correspond
to machine instructions.
Review: https://reviews.llvm.org/D68476
Patch authored by mgudim (Mikhail Gudim).
Diffstat (limited to 'llvm/lib/Target/AArch64')
-rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 379640eb5d3..af663f378d2 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -139,11 +139,11 @@ let Predicates = [HasSVE] in { defm FDIV_ZPmZ : sve_fp_2op_p_zds<0b1101, "fdiv">; defm FADD_ZZZ : sve_fp_3op_u_zd<0b000, "fadd", fadd>; - defm FSUB_ZZZ : sve_fp_3op_u_zd<0b001, "fsub", null_frag>; - defm FMUL_ZZZ : sve_fp_3op_u_zd<0b010, "fmul", null_frag>; + defm FSUB_ZZZ : sve_fp_3op_u_zd<0b001, "fsub", fsub>; + defm FMUL_ZZZ : sve_fp_3op_u_zd<0b010, "fmul", fmul>; defm FTSMUL_ZZZ : sve_fp_3op_u_zd<0b011, "ftsmul", null_frag>; - defm FRECPS_ZZZ : sve_fp_3op_u_zd<0b110, "frecps", null_frag>; - defm FRSQRTS_ZZZ : sve_fp_3op_u_zd<0b111, "frsqrts", null_frag>; + defm FRECPS_ZZZ : sve_fp_3op_u_zd<0b110, "frecps", int_aarch64_sve_frecps_x>; + defm FRSQRTS_ZZZ : sve_fp_3op_u_zd<0b111, "frsqrts", int_aarch64_sve_frsqrts_x>; defm FTSSEL_ZZZ : sve_int_bin_cons_misc_0_b<"ftssel">; |