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| author | Sander de Smalen <sander.desmalen@arm.com> | 2018-07-04 14:05:33 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2018-07-04 14:05:33 +0000 |
| commit | 1e4dc2e97d6cf6a8c13e90cf5cc9eec56a62e4f8 (patch) | |
| tree | 73d9a817f646ed3156db1cc273380313a9ae1cf6 /llvm/lib/Target/AArch64 | |
| parent | aef74139629dbece1f6b73969fb0601ec692e063 (diff) | |
| download | bcm5719-llvm-1e4dc2e97d6cf6a8c13e90cf5cc9eec56a62e4f8.tar.gz bcm5719-llvm-1e4dc2e97d6cf6a8c13e90cf5cc9eec56a62e4f8.zip | |
[AArch64][SVE] Asm: Support for reversed subtract (SUBR) instruction.
This patch adds both a vector and an immediate form, e.g.
- Vector form:
subr z0.h, p0/m, z0.h, z1.h
subtract active elements of z0 from z1, and store the result in z0.
- Immediate form:
subr z0.h, z0.h, #255
subtract elements of z0, and store the result in z0.
llvm-svn: 336274
Diffstat (limited to 'llvm/lib/Target/AArch64')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 7269e1e1983..ae818716af4 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -31,8 +31,9 @@ let Predicates = [HasSVE] in { def EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">; def BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">; - defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add">; - defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub">; + defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add">; + defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub">; + defm SUBR_ZPmZ : sve_int_bin_pred_arit_0<0b011, "subr">; defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr">; defm EOR_ZPmZ : sve_int_bin_pred_log<0b001, "eor">; @@ -41,6 +42,7 @@ let Predicates = [HasSVE] in { defm ADD_ZI : sve_int_arith_imm0<0b000, "add">; defm SUB_ZI : sve_int_arith_imm0<0b001, "sub">; + defm SUBR_ZI : sve_int_arith_imm0<0b011, "subr">; defm SQADD_ZI : sve_int_arith_imm0<0b100, "sqadd">; defm UQADD_ZI : sve_int_arith_imm0<0b101, "uqadd">; defm SQSUB_ZI : sve_int_arith_imm0<0b110, "sqsub">; |
