[C++] Use 'nullptr'. Target edition.

llvm-svn: 207197

8 files changed, 23 insertions, 23 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64BranchFixupPass.cpp b/llvm/lib/Target/AArch64/AArch64BranchFixupPass.cpp
index 1c65629908e..bff8ef50358 100644
--- a/llvm/lib/Target/AArch64/AArch64BranchFixupPass.cpp
+++ b/llvm/lib/Target/AArch64/AArch64BranchFixupPass.cpp
@@ -450,7 +450,7 @@ bool AArch64BranchFixup::isBBInRange(MachineInstr *MI,
 /// displacement field.
 bool AArch64BranchFixup::fixupImmediateBr(ImmBranch &Br) {
   MachineInstr *MI = Br.MI;
-  MachineBasicBlock *DestBB = 0;
+  MachineBasicBlock *DestBB = nullptr;
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     if (MI->getOperand(i).isMBB()) {
       DestBB = MI->getOperand(i).getMBB();
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index b2f8330306b..aab3d59697a 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -261,7 +261,7 @@ SDNode *AArch64DAGToDAGISel::TrySelectToMoveImm(SDNode *Node) {
   } else {
     // Can't handle it in one instruction. There's scope for permitting two (or
     // more) instructions, but that'll need more thought.
-    return NULL;
+    return nullptr;
   }
 
   ResNode = CurDAG->getMachineNode(MOVOpcode, dl, MOVType,
@@ -737,7 +737,7 @@ SDNode *AArch64DAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating,
   if (isUpdating)
     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
 
-  return NULL;
+  return nullptr;
 }
 
 SDNode *AArch64DAGToDAGISel::SelectVST(SDNode *N, bool isUpdating,
@@ -862,7 +862,7 @@ SDNode *AArch64DAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
   ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
   if (isUpdating)
     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
-  return NULL;
+  return nullptr;
 }
 
 // We only have 128-bit vector type of load/store lane instructions.
@@ -956,7 +956,7 @@ SDNode *AArch64DAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
   ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
   if (isUpdating)
     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
-  return NULL;
+  return nullptr;
 }
 
 unsigned AArch64DAGToDAGISel::getTBLOpc(bool IsExt, bool Is64Bit,
@@ -1031,7 +1031,7 @@ SDNode *AArch64DAGToDAGISel::Select(SDNode *Node) {
   if (Node->isMachineOpcode()) {
     DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");
     Node->setNodeId(-1);
-    return NULL;
+    return nullptr;
   }
 
   switch (Node->getOpcode()) {
@@ -1115,7 +1115,7 @@ SDNode *AArch64DAGToDAGISel::Select(SDNode *Node) {
                                 TFI, CurDAG->getTargetConstant(0, PtrTy));
   }
   case ISD::Constant: {
-    SDNode *ResNode = 0;
+    SDNode *ResNode = nullptr;
     if (cast<ConstantSDNode>(Node)->getZExtValue() == 0) {
       // XZR and WZR are probably even better than an actual move: most of the
       // time they can be folded into another instruction with *no* cost.
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index b1c31aa37f3..85df80613c4 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -589,7 +589,7 @@ static void getExclusiveOperation(unsigned Size, AtomicOrdering Ord,
 // would fail to figure out the register pressure correctly.
 std::pair<const TargetRegisterClass*, uint8_t>
 AArch64TargetLowering::findRepresentativeClass(MVT VT) const{
-  const TargetRegisterClass *RRC = 0;
+  const TargetRegisterClass *RRC = nullptr;
   uint8_t Cost = 1;
   switch (VT.SimpleTy) {
   default:
@@ -1185,7 +1185,7 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
   case AArch64ISD::NEON_VEXTRACT:
     return "AArch64ISD::NEON_VEXTRACT";
   default:
-    return NULL;
+    return nullptr;
   }
 }
 
@@ -2159,7 +2159,7 @@ AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
 
     // If softenSetCCOperands returned a scalar, we need to compare the result
     // against zero to select between true and false values.
-    if (RHS.getNode() == 0) {
+    if (!RHS.getNode()) {
       RHS = DAG.getConstant(0, LHS.getValueType());
       CC = ISD::SETNE;
     }
@@ -3019,7 +3019,7 @@ AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
     softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
 
     // If softenSetCCOperands returned a scalar, use it.
-    if (RHS.getNode() == 0) {
+    if (!RHS.getNode()) {
       assert(LHS.getValueType() == Op.getValueType() &&
              "Unexpected setcc expansion!");
       return LHS;
@@ -3167,7 +3167,7 @@ AArch64TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
 
     // If softenSetCCOperands returned a scalar, we need to compare the result
     // against zero to select between true and false values.
-    if (RHS.getNode() == 0) {
+    if (!RHS.getNode()) {
       RHS = DAG.getConstant(0, LHS.getValueType());
       CC = ISD::SETNE;
     }
@@ -4535,14 +4535,14 @@ bool AArch64TargetLowering::isKnownShuffleVector(SDValue Op, SelectionDAG &DAG,
             VT.getVectorElementType())
       return false;
 
-    if (V0.getNode() == 0) {
+    if (!V0.getNode()) {
       V0 = Elt.getOperand(0);
       V0NumElts = V0.getValueType().getVectorNumElements();
     }
     if (Elt.getOperand(0) == V0) {
       Mask[i] = (cast<ConstantSDNode>(Elt->getOperand(1))->getZExtValue());
       continue;
-    } else if (V1.getNode() == 0) {
+    } else if (!V1.getNode()) {
       V1 = Elt.getOperand(0);
     }
     if (Elt.getOperand(0) == V1) {
@@ -5243,7 +5243,7 @@ AArch64TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
                                                     std::string &Constraint,
                                                     std::vector<SDValue> &Ops,
                                                     SelectionDAG &DAG) const {
-  SDValue Result(0, 0);
+  SDValue Result;
 
   // Only length 1 constraints are C_Other.
   if (Constraint.size() != 1) return;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 6bc36030980..a39c1c5f258 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -391,10 +391,10 @@ AArch64InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                                MachineBasicBlock *FBB,
                                const SmallVectorImpl<MachineOperand> &Cond,
                                DebugLoc DL) const {
-  if (FBB == 0 && Cond.empty()) {
+  if (!FBB && Cond.empty()) {
     BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(TBB);
     return 1;
-  } else if (FBB == 0) {
+  } else if (!FBB) {
     MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
     for (int i = 1, e = Cond.size(); i != e; ++i)
       MIB.addOperand(Cond[i]);
diff --git a/llvm/lib/Target/AArch64/AArch64MCInstLower.cpp b/llvm/lib/Target/AArch64/AArch64MCInstLower.cpp
index 3842bfdab0d..103aeb00d87 100644
--- a/llvm/lib/Target/AArch64/AArch64MCInstLower.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MCInstLower.cpp
@@ -30,7 +30,7 @@ using namespace llvm;
 MCOperand
 AArch64AsmPrinter::lowerSymbolOperand(const MachineOperand &MO,
                                       const MCSymbol *Sym) const {
-  const MCExpr *Expr = 0;
+  const MCExpr *Expr = nullptr;
 
   Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, OutContext);
 
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index 5b45b1046c4..c37ffb59154 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -38,7 +38,7 @@ class AArch64TTI final : public ImmutablePass, public TargetTransformInfo {
   const AArch64TargetLowering *TLI;
 
 public:
-  AArch64TTI() : ImmutablePass(ID), ST(0), TLI(0) {
+  AArch64TTI() : ImmutablePass(ID), ST(nullptr), TLI(nullptr) {
     llvm_unreachable("This pass cannot be directly constructed");
   }
 
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 0b34d6a01a7..361f9848ce9 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1313,7 +1313,7 @@ AArch64AsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
   case AsmToken::Colon: {
     SMLoc StartLoc  = Parser.getTok().getLoc();
     SMLoc EndLoc;
-    const MCExpr *ImmVal = 0;
+    const MCExpr *ImmVal = nullptr;
 
     if (ParseImmediate(ImmVal) != MatchOperand_Success)
       return MatchOperand_ParseFail;
@@ -1325,7 +1325,7 @@ AArch64AsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
   case AsmToken::Hash: {   // Immediates
     SMLoc StartLoc = Parser.getTok().getLoc();
     SMLoc EndLoc;
-    const MCExpr *ImmVal = 0;
+    const MCExpr *ImmVal = nullptr;
     Parser.Lex();
 
     if (ParseImmediate(ImmVal) != MatchOperand_Success)
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
index c1e443e8681..9a104b70e03 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
@@ -63,7 +63,7 @@ static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
 
   MCAsmInfo *MAI = new AArch64ELFMCAsmInfo(TT);
   unsigned Reg = MRI.getDwarfRegNum(AArch64::XSP, true);
-  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, Reg, 0);
+  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
   MAI->addInitialFrameState(Inst);
 
   return MAI;
@@ -114,7 +114,7 @@ static MCInstPrinter *createAArch64MCInstPrinter(const Target &T,
                                                  const MCSubtargetInfo &STI) {
   if (SyntaxVariant == 0)
     return new AArch64InstPrinter(MAI, MII, MRI, STI);
-  return 0;
+  return nullptr;
 }
 
 namespace {