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| author | Victor Campos <victor.campos@arm.com> | 2019-10-18 12:40:29 +0000 |
|---|---|---|
| committer | Victor Campos <victor.campos@arm.com> | 2019-10-18 12:40:29 +0000 |
| commit | ffcd7698aea7bcbb2b4edffc484793e1ff47b85d (patch) | |
| tree | b9e27e9bc49164040b370c1c8d2fedf269d5d72e /llvm/lib/Target/AArch64/AArch64SystemOperands.td | |
| parent | 65f61c0030c5c375852f27ff6dd21e6a078e2420 (diff) | |
| download | bcm5719-llvm-ffcd7698aea7bcbb2b4edffc484793e1ff47b85d.tar.gz bcm5719-llvm-ffcd7698aea7bcbb2b4edffc484793e1ff47b85d.zip | |
[AArch64] Adding support for PMMIR_EL1 register
Summary:
The PMMIR_EL1 register is present in Armv8.4 with PMU extension.
This patch adds support for it.
Reviewers: t.p.northover, dnsampaio
Reviewed By: dnsampaio
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68940
llvm-svn: 375228
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64SystemOperands.td')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SystemOperands.td | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td index 2493be41765..05249a4ea6a 100644 --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -1322,6 +1322,12 @@ def : RWSysReg<"CNTHPS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b001>; def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>; } // FeatureSEL2 +// v8.4a PMU registers +// Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::FeaturePMU} }] in { +def : RWSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>; +} // FeaturePMU + // v8.4a RAS registers // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::FeatureRASv8_4} }] in { |
