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| author | Daniel Sanders <daniel_l_sanders@apple.com> | 2016-12-06 14:39:57 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel_l_sanders@apple.com> | 2016-12-06 14:39:57 +0000 |
| commit | 4fd1e7c628b6048b8c0f455bbe06b8c8c614335e (patch) | |
| tree | 2b8e2b854bf9116f1507753006eaa52e5de25338 /llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp | |
| parent | 1b8eb4104b6198785c164be4a451fc04e03bd371 (diff) | |
| download | bcm5719-llvm-4fd1e7c628b6048b8c0f455bbe06b8c8c614335e.tar.gz bcm5719-llvm-4fd1e7c628b6048b8c0f455bbe06b8c8c614335e.zip | |
[globalisel][aarch64] Fix unintended assumptions about PartialMappingIdx. NFC.
Summary:
This is NFC but prevents assertions when PartialMappingIdx is tablegen-erated.
The assumptions were:
1) FirstGPR is 0
2) FirstGPR is the first of the First* enumerators.
GPR32 is changed to 1 to demonstrate that assumption #1 is fixed. #2 will
be covered by a subsequent patch that tablegen-erates information and swaps
the order of GPR and FPR as a side effect.
Depends on D27336
Reviewers: ab, t.p.northover, qcolombet
Subscribers: aemerson, rengolin, vkalintiris, dberris, rovka, llvm-commits
Differential Revision: https://reviews.llvm.org/D27337
llvm-svn: 288812
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp index 0638b41b341..ef6c869e3ff 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -115,8 +115,9 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) #define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB) \ do { \ const PartialMapping &Map = \ - AArch64::PartMappings[AArch64::PartialMappingIdx::Idx]; \ - (void) Map; \ + AArch64::PartMappings[AArch64::PartialMappingIdx::Idx - \ + AArch64::PartialMappingIdx::PMI_Min]; \ + (void)Map; \ assert(Map.StartIdx == ValStartIdx && Map.Length == ValLength && \ Map.RegBank == &RB && #Idx " is incorrectly initialized"); \ } while (0) @@ -132,12 +133,13 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) // Check value mapping. #define CHECK_VALUEMAP_IMPL(RBName, Size, Offset) \ do { \ - AArch64::PartialMappingIdx PartialMapBaseIdx = \ - AArch64::PartialMappingIdx::PMI_##RBName##Size; \ - (void) PartialMapBaseIdx; \ - const ValueMapping &Map = \ - AArch64::getValueMapping(AArch64::PMI_First##RBName, Size)[Offset]; \ - (void) Map; \ + unsigned PartialMapBaseIdx = \ + AArch64::PartialMappingIdx::PMI_##RBName##Size - \ + AArch64::PartialMappingIdx::PMI_Min; \ + (void)PartialMapBaseIdx; \ + const ValueMapping &Map = AArch64::getValueMapping( \ + AArch64::PartialMappingIdx::PMI_First##RBName, Size)[Offset]; \ + (void)Map; \ assert(Map.BreakDown == &AArch64::PartMappings[PartialMapBaseIdx] && \ Map.NumBreakDowns == 1 && #RBName #Size \ " " #Offset " is incorrectly initialized"); \ @@ -172,10 +174,10 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) #define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size) \ do { \ - AArch64::PartialMappingIdx PartialMapDstIdx = \ - AArch64::PartialMappingIdx::PMI_##RBNameDst##Size; \ - AArch64::PartialMappingIdx PartialMapSrcIdx = \ - AArch64::PartialMappingIdx::PMI_##RBNameSrc##Size; \ + unsigned PartialMapDstIdx = \ + AArch64::PMI_##RBNameDst##Size - AArch64::PMI_Min; \ + unsigned PartialMapSrcIdx = \ + AArch64::PMI_##RBNameSrc##Size - AArch64::PMI_Min; \ (void) PartialMapDstIdx; \ (void) PartialMapSrcIdx; \ const ValueMapping *Map = AArch64::getCopyMapping( \ |
