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authorChad Rosier <mcrosier@codeaurora.org>2015-08-10 18:42:45 +0000
committerChad Rosier <mcrosier@codeaurora.org>2015-08-10 18:42:45 +0000
commitc56a9132d0e98b49f59f3b662bba2c293d6f3c73 (patch)
treecb628a7342daadea10dc2f642fadd13d79663b05 /llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
parent874b5c2197b21272a9a39ba149b4438c28b2d2eb (diff)
downloadbcm5719-llvm-c56a9132d0e98b49f59f3b662bba2c293d6f3c73.tar.gz
bcm5719-llvm-c56a9132d0e98b49f59f3b662bba2c293d6f3c73.zip
[AArch64] Convert a conditional check that will always be true to an assert. NFC.
llvm-svn: 244479
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp')
-rw-r--r--llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp10
1 files changed, 4 insertions, 6 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index d5a3c693105..b84eb36dc22 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -598,6 +598,7 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
}
if (CanMergeOpc && getLdStOffsetOp(MI).isImm()) {
+ assert(MI->mayLoadOrStore() && "Expected memory operation.");
// If we've found another instruction with the same opcode, check to see
// if the base and offset are compatible with our starting instruction.
// These instructions all have scaled immediate operands, so we just
@@ -623,8 +624,7 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
bool MIIsUnscaled = isUnscaledLdSt(MI);
if (!inBoundsForPair(MIIsUnscaled, MinOffset, OffsetStride)) {
trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
- if (MI->mayLoadOrStore())
- MemInsns.push_back(MI);
+ MemInsns.push_back(MI);
continue;
}
// If the alignment requirements of the paired (scaled) instruction
@@ -633,8 +633,7 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
if (IsUnscaled && EnableAArch64UnscaledMemOp &&
(alignTo(MinOffset, OffsetStride) != MinOffset)) {
trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
- if (MI->mayLoadOrStore())
- MemInsns.push_back(MI);
+ MemInsns.push_back(MI);
continue;
}
// If the destination register of the loads is the same register, bail
@@ -642,8 +641,7 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
// registers the same is UNPREDICTABLE and will result in an exception.
if (MayLoad && Reg == getLdStRegOp(MI).getReg()) {
trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
- if (MI->mayLoadOrStore())
- MemInsns.push_back(MI);
+ MemInsns.push_back(MI);
continue;
}
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