diff options
| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2017-03-27 17:31:48 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2017-03-27 17:31:48 +0000 |
| commit | 85a66a6d9fd5938fc617206f99761e06f0f1663d (patch) | |
| tree | 611d2f1cf924f3a8a7254eecae36fa2223b5cd78 /llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | |
| parent | ba3a4def29779b5ebb1533e66116bd4223f5aa9f (diff) | |
| download | bcm5719-llvm-85a66a6d9fd5938fc617206f99761e06f0f1663d.tar.gz bcm5719-llvm-85a66a6d9fd5938fc617206f99761e06f0f1663d.zip | |
[GlobalISel][AArch64] Select store of zero to WZR/XZR.
These occur very frequently, and are quite trivial to catch.
llvm-svn: 298862
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index 2e199d9c0d9..146eea07a56 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -775,6 +775,17 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { I.setDesc(TII.get(NewOpc)); I.addOperand(MachineOperand::CreateImm(0)); + + // If we're storing a 0, use WZR/XZR. + if (auto CVal = getConstantVRegVal(ValReg, MRI)) { + if (*CVal == 0 && Opcode == TargetOpcode::G_STORE) { + if (I.getOpcode() == AArch64::STRWui) + I.getOperand(0).setReg(AArch64::WZR); + else if (I.getOpcode() == AArch64::STRXui) + I.getOperand(0).setReg(AArch64::XZR); + } + } + return constrainSelectedInstRegOperands(I, TII, TRI, RBI); } |
