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authorNicola Zaghen <nicola.zaghen@imgtec.com>2018-05-14 12:53:11 +0000
committerNicola Zaghen <nicola.zaghen@imgtec.com>2018-05-14 12:53:11 +0000
commitd34e60ca8532511acb8c93ef26297e349fbec86a (patch)
tree1a095bc8694498d94232e81b95c1da05d462d3ec /llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
parentaffbc99bea94e77f7ebccd8ba887e33051bd04ee (diff)
downloadbcm5719-llvm-d34e60ca8532511acb8c93ef26297e349fbec86a.tar.gz
bcm5719-llvm-d34e60ca8532511acb8c93ef26297e349fbec86a.zip
Rename DEBUG macro to LLVM_DEBUG.
The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp')
-rw-r--r--llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp b/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
index 338daecb49e..22b0c1e3b47 100644
--- a/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
@@ -277,7 +277,7 @@ static MachineInstr *insertCopy(const TargetInstrInfo *TII, MachineInstr &MI,
MachineInstrBuilder MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
TII->get(AArch64::COPY), Dst)
.addReg(Src, getKillRegState(IsKill));
- DEBUG(dbgs() << " adding copy: " << *MIB);
+ LLVM_DEBUG(dbgs() << " adding copy: " << *MIB);
++NumCopiesInserted;
return MIB;
}
@@ -286,7 +286,7 @@ static MachineInstr *insertCopy(const TargetInstrInfo *TII, MachineInstr &MI,
// to its equivalant AdvSIMD scalar instruction. Update inputs and outputs
// to be the correct register class, minimizing cross-class copies.
void AArch64AdvSIMDScalar::transformInstruction(MachineInstr &MI) {
- DEBUG(dbgs() << "Scalar transform: " << MI);
+ LLVM_DEBUG(dbgs() << "Scalar transform: " << MI);
MachineBasicBlock *MBB = MI.getParent();
unsigned OldOpc = MI.getOpcode();
@@ -391,7 +391,7 @@ bool AArch64AdvSIMDScalar::processMachineBasicBlock(MachineBasicBlock *MBB) {
// runOnMachineFunction - Pass entry point from PassManager.
bool AArch64AdvSIMDScalar::runOnMachineFunction(MachineFunction &mf) {
bool Changed = false;
- DEBUG(dbgs() << "***** AArch64AdvSIMDScalar *****\n");
+ LLVM_DEBUG(dbgs() << "***** AArch64AdvSIMDScalar *****\n");
if (skipFunction(mf.getFunction()))
return false;
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