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| author | Kang Zhang <shkzhang@cn.ibm.com> | 2019-12-28 09:04:54 +0000 |
|---|---|---|
| committer | Kang Zhang <shkzhang@cn.ibm.com> | 2019-12-28 09:04:54 +0000 |
| commit | d1b51c5de7a0b7a7d81c3b520614a139eb0160d2 (patch) | |
| tree | 35eece1b18c31849b608ca797ea360e6f8a2259e /llvm/lib/TableGen | |
| parent | a3f896481329f64aac845e03cfda8f1154ce6079 (diff) | |
| download | bcm5719-llvm-d1b51c5de7a0b7a7d81c3b520614a139eb0160d2.tar.gz bcm5719-llvm-d1b51c5de7a0b7a7d81c3b520614a139eb0160d2.zip | |
[PowerPC] Modify the hasSideEffects of some VSX instructions from 1 to 0
Summary:
If we didn't set the value for hasSideEffects bit in our td file, `llvm-tblgen`
will set it as true for those instructions which has no match pattern.
Below 6 instructions don't set the hasSideEffects flag and don't have match
pattern, so their hasSideEffects flag will be set true by llvm-tblgen.
But in fact below instructions don't modify any special register and don't have
other SideEffects, they shouldn't have SideEffects.
This patch is to modify the hasSideEffects of below instructions from 1 to 0.
```
VEXTUHLX
VEXTUHRX
VEXTUWLX
VEXTUWRX
VSPLTBs
VSPLTHs
```
Reviewed By: jsji
Differential Revision: https://reviews.llvm.org/D71391
Diffstat (limited to 'llvm/lib/TableGen')
0 files changed, 0 insertions, 0 deletions
