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| author | Kang Zhang <shkzhang@cn.ibm.com> | 2019-12-28 09:04:54 +0000 |
|---|---|---|
| committer | Kang Zhang <shkzhang@cn.ibm.com> | 2019-12-28 09:04:54 +0000 |
| commit | d1b51c5de7a0b7a7d81c3b520614a139eb0160d2 (patch) | |
| tree | 35eece1b18c31849b608ca797ea360e6f8a2259e /llvm/lib | |
| parent | a3f896481329f64aac845e03cfda8f1154ce6079 (diff) | |
| download | bcm5719-llvm-d1b51c5de7a0b7a7d81c3b520614a139eb0160d2.tar.gz bcm5719-llvm-d1b51c5de7a0b7a7d81c3b520614a139eb0160d2.zip | |
[PowerPC] Modify the hasSideEffects of some VSX instructions from 1 to 0
Summary:
If we didn't set the value for hasSideEffects bit in our td file, `llvm-tblgen`
will set it as true for those instructions which has no match pattern.
Below 6 instructions don't set the hasSideEffects flag and don't have match
pattern, so their hasSideEffects flag will be set true by llvm-tblgen.
But in fact below instructions don't modify any special register and don't have
other SideEffects, they shouldn't have SideEffects.
This patch is to modify the hasSideEffects of below instructions from 1 to 0.
```
VEXTUHLX
VEXTUHRX
VEXTUWLX
VEXTUWRX
VSPLTBs
VSPLTHs
```
Reviewed By: jsji
Differential Revision: https://reviews.llvm.org/D71391
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index 21a432e7a53..1cdb4926101 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -711,7 +711,7 @@ def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), "vspltw $vD, $vB, $UIMM", IIC_VecPerm, [(set v16i8:$vD, (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>; -let isCodeGenOnly = 1 in { +let isCodeGenOnly = 1, hasSideEffects = 0 in { def VSPLTBs : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB), "vspltb $vD, $vB, $UIMM", IIC_VecPerm, []>; def VSPLTHs : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB), @@ -1378,12 +1378,14 @@ def VEXTRACTUW : VX1_VT5_UIM5_VB5<653, "vextractuw", []>; def VEXTRACTD : VX1_VT5_UIM5_VB5<717, "vextractd" , []>; // Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed +let hasSideEffects = 0 in { def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>; def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>; def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>; def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>; def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>; def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>; +} // Vector Insert Element Instructions def VINSERTB : VXForm_1<781, (outs vrrc:$vD), |
