From 18ccfadd4630878275f1142de7bd1b4e55ee2989 Mon Sep 17 00:00:00 2001 From: Hsiangkai Wang Date: Fri, 19 Jul 2019 02:03:34 +0000 Subject: [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame. It is necessary to generate fixups in .debug_frame or .eh_frame as relaxation is enabled due to the address delta may be changed after relaxation. There is an opcode with 6-bits data in debug frame encoding. So, we also need 6-bits fixup types. Differential Revision: https://reviews.llvm.org/D58335 llvm-svn: 366524 --- llvm/lib/Object/RelocationResolver.cpp | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'llvm/lib/Object/RelocationResolver.cpp') diff --git a/llvm/lib/Object/RelocationResolver.cpp b/llvm/lib/Object/RelocationResolver.cpp index 0a243f32e12..8738e2e9f3b 100644 --- a/llvm/lib/Object/RelocationResolver.cpp +++ b/llvm/lib/Object/RelocationResolver.cpp @@ -335,6 +335,8 @@ static bool supportsRISCV(uint64_t Type) { case ELF::R_RISCV_NONE: case ELF::R_RISCV_32: case ELF::R_RISCV_64: + case ELF::R_RISCV_SET6: + case ELF::R_RISCV_SUB6: case ELF::R_RISCV_ADD8: case ELF::R_RISCV_SUB8: case ELF::R_RISCV_ADD16: @@ -358,6 +360,10 @@ static uint64_t resolveRISCV(RelocationRef R, uint64_t S, uint64_t A) { return (S + RA) & 0xFFFFFFFF; case ELF::R_RISCV_64: return S + RA; + case ELF::R_RISCV_SET6: + return (A + (S + RA)) & 0xFF; + case ELF::R_RISCV_SUB6: + return (A - (S + RA)) & 0xFF; case ELF::R_RISCV_ADD8: return (A + (S + RA)) & 0xFF; case ELF::R_RISCV_SUB8: -- cgit v1.2.3