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authorAlkis Evlogimenos <alkis@evlogimenos.com>2004-01-05 02:25:45 +0000
committerAlkis Evlogimenos <alkis@evlogimenos.com>2004-01-05 02:25:45 +0000
commit08c5311729b684619e307b561fbecc0095e85bfe (patch)
treeccc0a087ff1c6a3858b6682d40ea2e300335220e /llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
parent5e0e67173db72011cff3c9ad2d1e8962a45fd957 (diff)
downloadbcm5719-llvm-08c5311729b684619e307b561fbecc0095e85bfe.tar.gz
bcm5719-llvm-08c5311729b684619e307b561fbecc0095e85bfe.zip
Currently we cannot handle two-address instructions of the form:
A = B op C where A == C, but this cannot really occur in practice because of SSA form. Add an assert to check that just to be safe. llvm-svn: 10682
Diffstat (limited to 'llvm/lib/CodeGen/TwoAddressInstructionPass.cpp')
-rw-r--r--llvm/lib/CodeGen/TwoAddressInstructionPass.cpp9
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 41b3cbd8ed1..b758e7fd224 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -123,6 +123,15 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &fn) {
bool regAisPhysical = regA < MRegisterInfo::FirstVirtualRegister;
bool regBisPhysical = regB < MRegisterInfo::FirstVirtualRegister;
+ // first make sure we do not have a use of a in the
+ // instruction (a = b + a for example) because our
+ // transofrmation will not work. This should never occur
+ // because of SSA.
+ for (unsigned i = 1; i < mi->getNumOperands(); ++i) {
+ assert(!mi->getOperand(i).isRegister() ||
+ mi->getOperand(i).getAllocatedRegNum() != regA);
+ }
+
const TargetRegisterClass* rc = regAisPhysical ?
mri_->getRegClass(regA) :
mf_->getSSARegMap()->getRegClass(regA);
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