From 08c5311729b684619e307b561fbecc0095e85bfe Mon Sep 17 00:00:00 2001 From: Alkis Evlogimenos Date: Mon, 5 Jan 2004 02:25:45 +0000 Subject: Currently we cannot handle two-address instructions of the form: A = B op C where A == C, but this cannot really occur in practice because of SSA form. Add an assert to check that just to be safe. llvm-svn: 10682 --- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'llvm/lib/CodeGen/TwoAddressInstructionPass.cpp') diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index 41b3cbd8ed1..b758e7fd224 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -123,6 +123,15 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &fn) { bool regAisPhysical = regA < MRegisterInfo::FirstVirtualRegister; bool regBisPhysical = regB < MRegisterInfo::FirstVirtualRegister; + // first make sure we do not have a use of a in the + // instruction (a = b + a for example) because our + // transofrmation will not work. This should never occur + // because of SSA. + for (unsigned i = 1; i < mi->getNumOperands(); ++i) { + assert(!mi->getOperand(i).isRegister() || + mi->getOperand(i).getAllocatedRegNum() != regA); + } + const TargetRegisterClass* rc = regAisPhysical ? mri_->getRegClass(regA) : mf_->getSSARegMap()->getRegClass(regA); -- cgit v1.2.3