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| author | MinSeong Kim <min.s.kim@samsung.com> | 2016-01-05 14:50:15 +0000 |
|---|---|---|
| committer | MinSeong Kim <min.s.kim@samsung.com> | 2016-01-05 14:50:15 +0000 |
| commit | 4a9a4e198f666330690f524d3109e08471c606f6 (patch) | |
| tree | ff0a6204260fdfcd120aa359c55970444132f1e4 /llvm/lib/CodeGen/TargetSchedule.cpp | |
| parent | cf04d04ccf6879aa943e09ca8066105e692ab2df (diff) | |
| download | bcm5719-llvm-4a9a4e198f666330690f524d3109e08471c606f6.tar.gz bcm5719-llvm-4a9a4e198f666330690f524d3109e08471c606f6.zip | |
[MISched] Explanatory error message when machine model is not complete. NFC
When not all instructions have a scheduling class,
the error message now provides a possible solution.
Differential Revision: http://reviews.llvm.org/D15854
llvm-svn: 256839
Diffstat (limited to 'llvm/lib/CodeGen/TargetSchedule.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/TargetSchedule.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/TargetSchedule.cpp b/llvm/lib/CodeGen/TargetSchedule.cpp index fc656396ade..1c4558cea5f 100644 --- a/llvm/lib/CodeGen/TargetSchedule.cpp +++ b/llvm/lib/CodeGen/TargetSchedule.cpp @@ -212,7 +212,7 @@ unsigned TargetSchedModel::computeOperandLatency( && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() && SchedModel.isComplete()) { errs() << "DefIdx " << DefIdx << " exceeds machine model writes for " - << *DefMI; + << *DefMI << " (Try with MCSchedModel.CompleteModel set to false)"; llvm_unreachable("incomplete machine model"); } #endif |
