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| author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2016-07-06 09:01:20 +0000 |
|---|---|---|
| committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2016-07-06 09:01:20 +0000 |
| commit | 5a4f2476fd960e85c100f939aac548d9f167fc7e (patch) | |
| tree | 87054eb34bc1388d5d52d12e2cdc053e6dbb5891 /llvm/lib/CodeGen/TargetRegisterInfo.cpp | |
| parent | e40530ea7b594d80decb6feca902f02cc9d620f6 (diff) | |
| download | bcm5719-llvm-5a4f2476fd960e85c100f939aac548d9f167fc7e.tar.gz bcm5719-llvm-5a4f2476fd960e85c100f939aac548d9f167fc7e.zip | |
AVX-512: Optimization for patterns with i1 scalar type
The patch removes redundant kmov instructions (not all, we still have a lot of work here) and redundant "and" instructions after "setcc".
I use "AssertZero" marker between X86ISD::SETCC node and "truncate" to eliminate extra "and $1" instruction.
I also changed zext, aext and trunc patterns in the .td file. It allows to remove extra "kmov" instruictions.
This patch fixes https://llvm.org/bugs/show_bug.cgi?id=28173.
Fast ISEL mode is not supported correctly for AVX-512. ICMP/FCMP scalar instruction should return result in k-reg. It will be fixed in one of the next patches. I redirected handling of "cmp" to the DAG builder mode. (The code looks worse in one specific test case, but without this fix the new patch fails).
Differential revision: http://reviews.llvm.org/D21956
llvm-svn: 274613
Diffstat (limited to 'llvm/lib/CodeGen/TargetRegisterInfo.cpp')
0 files changed, 0 insertions, 0 deletions
