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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-08-14 19:54:47 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-08-14 19:54:47 +0000 |
| commit | 81da0d45f857dfd10f87be5c60008afdf7f7d02e (patch) | |
| tree | 5e99ffb00fe5d331ffd3122bdb707691740c340e /llvm/lib/CodeGen/TargetPassConfig.cpp | |
| parent | f9273c81d60b6878dff479c5b5fae432525e202c (diff) | |
| download | bcm5719-llvm-81da0d45f857dfd10f87be5c60008afdf7f7d02e.tar.gz bcm5719-llvm-81da0d45f857dfd10f87be5c60008afdf7f7d02e.zip | |
IPRA: Allow target to enable IPRA by default
llvm-svn: 310876
Diffstat (limited to 'llvm/lib/CodeGen/TargetPassConfig.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/TargetPassConfig.cpp | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp index 75a565e898f..481baea2dff 100644 --- a/llvm/lib/CodeGen/TargetPassConfig.cpp +++ b/llvm/lib/CodeGen/TargetPassConfig.cpp @@ -47,6 +47,9 @@ using namespace llvm; +cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, + cl::desc("Enable interprocedural register allocation " + "to reduce load/store at procedure calls.")); static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler")); static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden, @@ -362,6 +365,13 @@ TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm) if (StringRef(PrintMachineInstrs.getValue()).equals("")) TM.Options.PrintMachineCode = true; + if (EnableIPRA.getNumOccurrences()) + TM.Options.EnableIPRA = EnableIPRA; + else { + // If not explicitly specified, use target default. + TM.Options.EnableIPRA = TM.useIPRA(); + } + if (TM.Options.EnableIPRA) setRequiresCodeGenSCCOrder(); |
