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authorMatt Arsenault <Matthew.Arsenault@amd.com>2017-08-14 19:54:45 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2017-08-14 19:54:45 +0000
commitf9273c81d60b6878dff479c5b5fae432525e202c (patch)
treedf15347fcc5036e858425711692386cd34de2f1a /llvm/lib/CodeGen/TargetPassConfig.cpp
parent8b352c4d9d8266c538cdf2fa4c8a8ccb52411207 (diff)
downloadbcm5719-llvm-f9273c81d60b6878dff479c5b5fae432525e202c.tar.gz
bcm5719-llvm-f9273c81d60b6878dff479c5b5fae432525e202c.zip
IPRA: Run RegUsageInfoPropagate much later
This was running immediately after isel, before isel pseudos were even expanded which is really unreasonable. Move this to before pre-reglloc passes in case some other pre-regalloc pass wants to use the updated regmask info. Fixes one of the reasons IPRA doesn't do anything on AMDGPU currently. Tests will be included with future patch after a few more are fixed. llvm-svn: 310875
Diffstat (limited to 'llvm/lib/CodeGen/TargetPassConfig.cpp')
-rw-r--r--llvm/lib/CodeGen/TargetPassConfig.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp
index de0d2264de2..75a565e898f 100644
--- a/llvm/lib/CodeGen/TargetPassConfig.cpp
+++ b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -779,9 +779,6 @@ void TargetPassConfig::addMachinePasses() {
// Print the instruction selected machine code...
printAndVerify("After Instruction Selection");
- if (TM->Options.EnableIPRA)
- addPass(createRegUsageInfoPropPass());
-
// Expand pseudo-instructions emitted by ISel.
addPass(&ExpandISelPseudosID);
@@ -794,6 +791,9 @@ void TargetPassConfig::addMachinePasses() {
addPass(&LocalStackSlotAllocationID, false);
}
+ if (TM->Options.EnableIPRA)
+ addPass(createRegUsageInfoPropPass());
+
// Run pre-ra passes.
addPreRegAlloc();
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