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| author | Oliver Stannard <oliver.stannard@linaro.org> | 2019-08-02 10:23:17 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@linaro.org> | 2019-08-02 10:23:17 +0000 |
| commit | 4b7239ebaca72f2cd92682019fbe0bef5b46cd4e (patch) | |
| tree | 9e69d9d57dd2290f21ab73a63cf156a676e4cf36 /llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp | |
| parent | f6b00c279a5587a25876752a6ecd8da0bed959dc (diff) | |
| download | bcm5719-llvm-4b7239ebaca72f2cd92682019fbe0bef5b46cd4e.tar.gz bcm5719-llvm-4b7239ebaca72f2cd92682019fbe0bef5b46cd4e.zip | |
[IPRA][ARM] Disable no-CSR optimisation for ARM
This optimisation isn't generally profitable for ARM, because we can
save/restore many registers in the prologue and epilogue using the PUSH
and POP instructions, but mostly use individual LDR/STR instructions for
other spills.
Differential revision: https://reviews.llvm.org/D64910
llvm-svn: 367670
Diffstat (limited to 'llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp index 9c4483cb240..c5cd87b1481 100644 --- a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp +++ b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp @@ -71,7 +71,9 @@ void TargetFrameLowering::determineCalleeSaves(MachineFunction &MF, // When interprocedural register allocation is enabled caller saved registers // are preferred over callee saved registers. - if (MF.getTarget().Options.EnableIPRA && isSafeForNoCSROpt(MF.getFunction())) + if (MF.getTarget().Options.EnableIPRA && + isSafeForNoCSROpt(MF.getFunction()) && + isProfitableForNoCSROpt(MF.getFunction())) return; // Get the callee saved register list... |
