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| author | Oliver Stannard <oliver.stannard@linaro.org> | 2019-08-02 10:23:05 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@linaro.org> | 2019-08-02 10:23:05 +0000 |
| commit | f6b00c279a5587a25876752a6ecd8da0bed959dc (patch) | |
| tree | e9984f3502ad3cdee3ec7e445cd4b5e1cc735a62 /llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp | |
| parent | de67affd005d2a4af3554ff48f874868f022a022 (diff) | |
| download | bcm5719-llvm-f6b00c279a5587a25876752a6ecd8da0bed959dc.tar.gz bcm5719-llvm-f6b00c279a5587a25876752a6ecd8da0bed959dc.zip | |
Fix and test inter-procedural register allocation for ARM
- Avoid a crash when IPRA calls ARMFrameLowering::determineCalleeSaves
with a null RegScavenger. Simply not updating the register scavenger
is fine because IPRA only cares about the SavedRegs vector, the acutal
code of the function has already been generated at this point.
- Add a new hook to TargetRegisterInfo to get the set of registers which
can be clobbered inside a call, even if the compiler can see both
sides, by linker-generated code.
Differential revision: https://reviews.llvm.org/D64908
llvm-svn: 367669
Diffstat (limited to 'llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp')
0 files changed, 0 insertions, 0 deletions
