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authorScott Michel <scottm@aero.org>2009-01-21 04:58:48 +0000
committerScott Michel <scottm@aero.org>2009-01-21 04:58:48 +0000
commited7d79fce4ed71e21d8492d144edf0c19cecf080 (patch)
tree50f468a35e35c7c4c980fafffc79538b438bdf4d /llvm/lib/CodeGen/SelectionDAG
parenta70798cc9ab10106649819222840600cd703158b (diff)
downloadbcm5719-llvm-ed7d79fce4ed71e21d8492d144edf0c19cecf080.tar.gz
bcm5719-llvm-ed7d79fce4ed71e21d8492d144edf0c19cecf080.zip
CellSPU:
- Ensure that (operation) legalization emits proper FDIV libcall when needed. - Fix various bugs encountered during llvm-spu-gcc build, along with various cleanups. - Start supporting double precision comparisons for remaining libgcc2 build. Discovered interesting DAGCombiner feature, which is currently solved via custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner insists on inserting one anyway.) - Update README. llvm-svn: 62664
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 258d807f701..608dde21444 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3294,6 +3294,10 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
RTLIB::POW_PPCF128);
break;
+ case ISD::FDIV:
+ LC = GetFPLibCall(VT, RTLIB::DIV_F32, RTLIB::DIV_F64, RTLIB::DIV_F80,
+ RTLIB::DIV_PPCF128);
+ break;
default: break;
}
if (LC != RTLIB::UNKNOWN_LIBCALL) {
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