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authorEric Christopher <echristo@apple.com>2012-07-02 21:16:43 +0000
committerEric Christopher <echristo@apple.com>2012-07-02 21:16:43 +0000
commitdd8638fb3e172da32e0ed3e30ac80535b40c054e (patch)
tree6cfb94a5a7c806ef194153f10352bae7ee08f6a1 /llvm/lib/CodeGen/SelectionDAG
parent6e80d5934d1b2b5c9df25500025a3c46c8238794 (diff)
downloadbcm5719-llvm-dd8638fb3e172da32e0ed3e30ac80535b40c054e.tar.gz
bcm5719-llvm-dd8638fb3e172da32e0ed3e30ac80535b40c054e.zip
Turn an assert into an error to make it a bit more friendly.
Part of rdar://6880388 and rdar://11766377 llvm-svn: 159590
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp11
1 files changed, 9 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 72e57696ded..4fd95e92b9c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -6250,8 +6250,15 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
OpInfo.ConstraintType == TargetLowering::C_Register) &&
"Unknown constraint type!");
- assert(!OpInfo.isIndirect &&
- "Don't know how to handle indirect register inputs yet!");
+
+ // TODO: Support this.
+ if (OpInfo.isIndirect) {
+ LLVMContext &Ctx = *DAG.getContext();
+ Ctx.emitError(CS.getInstruction(),
+ "Don't know how to handle indirect register inputs yet "
+ "for constraint '" + Twine(OpInfo.ConstraintCode) + "'");
+ break;
+ }
// Copy the input into the appropriate registers.
if (OpInfo.AssignedRegs.Regs.empty()) {
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