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author | Alp Toker <alp@nuanti.com> | 2014-01-24 17:20:08 +0000 |
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committer | Alp Toker <alp@nuanti.com> | 2014-01-24 17:20:08 +0000 |
commit | cb4029110040c3655a66b5f423d328c749ba6a49 (patch) | |
tree | ff63cddc3870db1526fd120a14aa690e186239b9 /llvm/lib/CodeGen/SelectionDAG | |
parent | ad6aa47c20ae7412873029fc6e611b05dc169e10 (diff) | |
download | bcm5719-llvm-cb4029110040c3655a66b5f423d328c749ba6a49.tar.gz bcm5719-llvm-cb4029110040c3655a66b5f423d328c749ba6a49.zip |
Fix known typos
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.
llvm-svn: 200018
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index dd67b45e728..2dafcb9fa97 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -6740,7 +6740,7 @@ SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0); } - // The next optimizations are desireable only if SELECT_CC can be lowered. + // The next optimizations are desirable only if SELECT_CC can be lowered. // Check against MVT::Other for SELECT_CC, which is a workaround for targets // having to say they don't support SELECT_CC on every type the DAG knows // about, since there is no way to mark an opcode illegal at all value types @@ -6797,7 +6797,7 @@ SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0); } - // The next optimizations are desireable only if SELECT_CC can be lowered. + // The next optimizations are desirable only if SELECT_CC can be lowered. // Check against MVT::Other for SELECT_CC, which is a workaround for targets // having to say they don't support SELECT_CC on every type the DAG knows // about, since there is no way to mark an opcode illegal at all value types @@ -8265,7 +8265,7 @@ bool DAGCombiner::SliceUpLoad(SDNode *N) { // The width of the type must be a power of 2 and greater than 8-bits. // Otherwise the load cannot be represented in LLVM IR. // Moreover, if we shifted with a non-8-bits multiple, the slice - // will be accross several bytes. We do not support that. + // will be across several bytes. We do not support that. unsigned Width = User->getValueSizeInBits(0); if (Width < 8 || !isPowerOf2_32(Width) || (Shift & 0x7)) return 0; |