summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG
diff options
context:
space:
mode:
authorSimon Pilgrim <llvm-dev@redking.me.uk>2017-07-19 13:39:58 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2017-07-19 13:39:58 +0000
commitc77e2622607689a4c813d875e8233cb8ebeeb6a7 (patch)
treea239ef37bd1ded95d63b3570370175926c749e7a /llvm/lib/CodeGen/SelectionDAG
parent4c5fd9cd7f758f563eeb30cbe23708074d8f80b2 (diff)
downloadbcm5719-llvm-c77e2622607689a4c813d875e8233cb8ebeeb6a7.tar.gz
bcm5719-llvm-c77e2622607689a4c813d875e8233cb8ebeeb6a7.zip
{DAGCombine] Convert (Val & Mask) == Mask to Mask.isSubsetof(Val). NFCI.
llvm-svn: 308460
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d5d3f7a61a9..847d6d8e677 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7854,7 +7854,7 @@ SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
case ISD::AND: {
// X & -1 -> X (ignoring bits which aren't demanded).
ConstantSDNode *AndVal = isConstOrConstSplat(V.getOperand(1));
- if (AndVal && (AndVal->getAPIntValue() & Mask) == Mask)
+ if (AndVal && Mask.isSubsetOf(AndVal->getAPIntValue()))
return V.getOperand(0);
break;
}
OpenPOWER on IntegriCloud