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| author | Evan Cheng <evan.cheng@apple.com> | 2012-07-11 18:55:07 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2012-07-11 18:55:07 +0000 |
| commit | b17122859be828b3d0a7fa787b4ade2258edd473 (patch) | |
| tree | 3ea7343e9ef170e81462cd8984112e26e1258d70 /llvm/lib/CodeGen/SelectionDAG | |
| parent | 3aab6a86a263369fc49a6180f9163d0077435a02 (diff) | |
| download | bcm5719-llvm-b17122859be828b3d0a7fa787b4ade2258edd473.tar.gz bcm5719-llvm-b17122859be828b3d0a7fa787b4ade2258edd473.zip | |
InstrEmitter::EmitSubregNode() optimize extract_subreg in this case:
r1025 = s/zext r1024, 4
r1026 = extract_subreg r1025, 4
to a copy:
r1026 = copy r1024
This is correct. However it uses TII->isCoalescableExtInstr() which can return
true for instructions which essentially does a sext_in_reg so this can end up
with an illegal copy where the source and destination register classes do not
match. Add a check to avoid it. Sorry, no test case possible at this time.
rdar://11849816
llvm-svn: 160059
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index 578b51d9f86..936c1269a8c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -479,7 +479,8 @@ void InstrEmitter::EmitSubregNode(SDNode *Node, unsigned SrcReg, DstReg, DefSubIdx; if (DefMI && TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && - SubIdx == DefSubIdx) { + SubIdx == DefSubIdx && + TRC == MRI->getRegClass(SrcReg)) { // Optimize these: // r1025 = s/zext r1024, 4 // r1026 = extract_subreg r1025, 4 |
