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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-02 05:43:46 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-02 05:43:46 +0000 |
| commit | aff10602072d77d974280f98fb6020c5ed70d4b0 (patch) | |
| tree | 80a120acb0fdbb41fc0ef51758eea9a5330f60e6 /llvm/lib/CodeGen/SelectionDAG | |
| parent | 7f25c32d5b7b232dbce76d0b57817bc335a54ab1 (diff) | |
| download | bcm5719-llvm-aff10602072d77d974280f98fb6020c5ed70d4b0.tar.gz bcm5719-llvm-aff10602072d77d974280f98fb6020c5ed70d4b0.zip | |
Use TRI::has{Sub,Super}ClassEq() where possible.
No functional change.
llvm-svn: 132455
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index e309defba20..cb49a80b67e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -283,7 +283,7 @@ InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op, DstRC = II->OpInfo[IIOpNum].getRegClass(TRI); assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) && "Don't have operand info for this instruction!"); - if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) { + if (DstRC && !SrcRC->hasSuperClassEq(DstRC)) { unsigned NewVReg = MRI->createVirtualRegister(DstRC); BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); |
