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authorMatt Arsenault <Matthew.Arsenault@amd.com>2017-08-02 00:43:42 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2017-08-02 00:43:42 +0000
commitacc5e82b0e33a27ba64ccb4f88c81fe8709d4576 (patch)
treede36eb055031183f0de7f2f65c688c27091bb987 /llvm/lib/CodeGen/SelectionDAG
parent6b898beb8e6bf5739d43c1d64646264afc595de8 (diff)
downloadbcm5719-llvm-acc5e82b0e33a27ba64ccb4f88c81fe8709d4576.tar.gz
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DAG: Undo and->or combine with FrameIndexes
This pattern shows up when lowering byval copies on AMDGPU. The byval object access is split into 4-byte chunks, adding a constant offset to the FixedStack base. When some of the offsets turn into ors, this prevents combining the constant offsets. This makes it not apparent that the object is there when matching addressing modes, so it ends up using a scratch wave offset relative access and the lengthy frame index expansion for that. llvm-svn: 309775
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp9
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 54cddf77b4c..cf19d7b4fc0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1947,6 +1947,15 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Not);
}
}
+
+ // Undo the add -> or combine to merge constant offsets from a frame index.
+ if (N0.getOpcode() == ISD::OR &&
+ isa<FrameIndexSDNode>(N0.getOperand(0)) &&
+ isa<ConstantSDNode>(N0.getOperand(1)) &&
+ DAG.haveNoCommonBitsSet(N0.getOperand(0), N0.getOperand(1))) {
+ SDValue Add0 = DAG.getNode(ISD::ADD, DL, VT, N1, N0.getOperand(1));
+ return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Add0);
+ }
}
if (SDValue NewSel = foldBinOpIntoSelect(N))
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