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authorEvan Cheng <evan.cheng@apple.com>2009-07-21 05:40:15 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-07-21 05:40:15 +0000
commita7bb55ebb615001f5ca871713c5c98014e5ed2b4 (patch)
treec331e4d8e1c90bd6cf70e626dc82d9cc6aa2a99c /llvm/lib/CodeGen/SelectionDAG
parentf319a7d6e781be2f576533d5007da123a1b697eb (diff)
downloadbcm5719-llvm-a7bb55ebb615001f5ca871713c5c98014e5ed2b4.tar.gz
bcm5719-llvm-a7bb55ebb615001f5ca871713c5c98014e5ed2b4.zip
Fix a dagga combiner bug: avoid creating illegal constant.
Is this really a winning transformation? fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or (srl (and x, (shl -1, c1)), (sub c1, c2)) llvm-svn: 76535
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp21
1 files changed, 12 insertions, 9 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 4ff2a3adedb..370054d296c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2475,15 +2475,18 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
if (N1C && N0.getOpcode() == ISD::SRL &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
- uint64_t c2 = N1C->getZExtValue();
- SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, N0.getOperand(0),
- DAG.getConstant(~0ULL << c1, VT));
- if (c2 > c1)
- return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
- DAG.getConstant(c2-c1, N1.getValueType()));
- else
- return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
- DAG.getConstant(c1-c2, N1.getValueType()));
+ if (c1 < VT.getSizeInBits()) {
+ uint64_t c2 = N1C->getZExtValue();
+ SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT,
+ N0.getOperand(0),
+ DAG.getConstant(~0ULL << c1, VT));
+ if (c2 > c1)
+ return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
+ DAG.getConstant(c2-c1, N1.getValueType()));
+ else
+ return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
+ DAG.getConstant(c1-c2, N1.getValueType()));
+ }
}
// fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
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