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| author | Oliver Stannard <oliver.stannard@arm.com> | 2014-11-05 12:06:39 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2014-11-05 12:06:39 +0000 |
| commit | 9e89d8cc5cd048b5ed2037f472f3d38ce2c8328f (patch) | |
| tree | 885f70aaf959a2338916c3c23aee98c8bea4614d /llvm/lib/CodeGen/SelectionDAG | |
| parent | e20ce07a2fa6c447872da3f8230c08e46166d9e3 (diff) | |
| download | bcm5719-llvm-9e89d8cc5cd048b5ed2037f472f3d38ce2c8328f.tar.gz bcm5719-llvm-9e89d8cc5cd048b5ed2037f472f3d38ce2c8328f.zip | |
[ARM] Honor FeatureD16 in the assembler and disassembler
Some ARM FPUs only have 16 double-precision registers, rather than the
normal 32. LLVM represents this with the D16 target feature. This is
currently used by CodeGen to avoid using high registers when they are
not available, but the assembler and disassembler do not.
I fix this in the assmebler and disassembler rather than the
InstrInfo.td files, as the latter would require a large number of
changes everywhere one of the floating-point instructions is referenced
in the backend. This solution is similar to the one used for
co-processor numbers and MSR masks.
llvm-svn: 221341
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
0 files changed, 0 insertions, 0 deletions
