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| author | Dan Gohman <gohman@apple.com> | 2009-03-31 01:38:29 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-03-31 01:38:29 +0000 |
| commit | 97a20b8dbf23d6a952576da1c1c251d329b51c40 (patch) | |
| tree | 4723d2eb42eca4a23a5095dfa0e95a6c263f58b4 /llvm/lib/CodeGen/SelectionDAG | |
| parent | 885bc6de525472980c7651c3d835dbe7005dc63f (diff) | |
| download | bcm5719-llvm-97a20b8dbf23d6a952576da1c1c251d329b51c40.tar.gz bcm5719-llvm-97a20b8dbf23d6a952576da1c1c251d329b51c40.zip | |
Fix live-out reg logic to not insert over-aggressive AssertZExt
instructions. This fixes lua.
llvm-svn: 68083
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index 4bf90508e9f..ba59906b6da 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -4587,15 +4587,15 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 else if (NumSignBits > RegSize-8) isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 - else if (NumZeroBits >= RegSize-9) + else if (NumZeroBits >= RegSize-8) isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 else if (NumSignBits > RegSize-16) isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 - else if (NumZeroBits >= RegSize-17) + else if (NumZeroBits >= RegSize-16) isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 else if (NumSignBits > RegSize-32) isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 - else if (NumZeroBits >= RegSize-33) + else if (NumZeroBits >= RegSize-32) isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 if (FromVT != MVT::Other) { |
