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| author | Craig Topper <craig.topper@intel.com> | 2019-04-05 06:32:50 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-04-05 06:32:50 +0000 |
| commit | 94f1772b1e517ba0ea47150eca27f3fe9366f2ec (patch) | |
| tree | f61bce6e9883b241ba60edab7266c7e09fe549d8 /llvm/lib/CodeGen/SelectionDAG | |
| parent | c39636cc2c6d17453bca3d76cdaba4a458b45ae3 (diff) | |
| download | bcm5719-llvm-94f1772b1e517ba0ea47150eca27f3fe9366f2ec.tar.gz bcm5719-llvm-94f1772b1e517ba0ea47150eca27f3fe9366f2ec.zip | |
[X86] Promote i16 SRA instructions to i32
We already promote SRL and SHL to i32.
This will introduce sign extends sometimes which might be harder to deal with than the zero we use for promoting SRL. I ran this through some of our internal benchmark lists and didn't see any major regressions.
I think there might be some DAG combine improvement opportunities in the test changes here.
Differential Revision: https://reviews.llvm.org/D60278
llvm-svn: 357743
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
0 files changed, 0 insertions, 0 deletions
