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authorSanjay Patel <spatel@rotateright.com>2019-12-12 16:19:37 -0500
committerSanjay Patel <spatel@rotateright.com>2019-12-12 16:24:40 -0500
commit9432937190d8c891a93521bed7b9b76397e410e3 (patch)
tree7add16c9ab518dae7ea8ed224b33ab52265b9774 /llvm/lib/CodeGen/SelectionDAG
parent4c6c1d0f437194904d6093ca2f94230b6ec49e0b (diff)
downloadbcm5719-llvm-9432937190d8c891a93521bed7b9b76397e410e3.tar.gz
bcm5719-llvm-9432937190d8c891a93521bed7b9b76397e410e3.zip
Revert "[DAGCombiner] fold shift-trunc-shift to shift-mask-trunc"
This reverts commit 8963332c3327daa652ba3e26d35f9109b6991985. There was a logic bug typo in this code, but it wasn't visible in the asm for the tests.
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp12
1 files changed, 0 insertions, 12 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index fdc9f48fbcc..c462a6bcb9f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7943,18 +7943,6 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
InnerShift.getOperand(0), NewShiftAmt);
return DAG.getNode(ISD::TRUNCATE, DL, VT, NewShift);
}
- // In the more general case, we can clear the high bits after the shift:
- // srl (trunc (srl x, c1)), c2 --> trunc (and (srl x, (c1+c2)), Mask)
- if (N0.hasOneUse() && InnerShift.hasOneUse() && c1 + c2 <= OpSizeInBits) {
- SDLoc DL(N);
- SDValue NewShiftAmt = DAG.getConstant(c1 + c2, DL, ShiftAmtVT);
- SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT,
- InnerShift.getOperand(0), NewShiftAmt);
- SDValue Mask = DAG.getConstant((1 << (InnerShiftSize - c2)) - 1, DL,
- InnerShiftVT);
- SDValue And = DAG.getNode(ISD::AND, DL, InnerShiftVT, NewShift, Mask);
- return DAG.getNode(ISD::TRUNCATE, DL, VT, And);
- }
}
}
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