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authorCraig Topper <craig.topper@intel.com>2019-02-20 20:52:26 +0000
committerCraig Topper <craig.topper@intel.com>2019-02-20 20:52:26 +0000
commit8d9c224a8c5fc3a5a48e6406ccbfc2c2d68128b2 (patch)
treeb32ad158db8b9af503cf9e8cfdb4da61190b22f7 /llvm/lib/CodeGen/SelectionDAG
parentc3b496de7abf7d43c870d092a56969a4fee5fa96 (diff)
downloadbcm5719-llvm-8d9c224a8c5fc3a5a48e6406ccbfc2c2d68128b2.tar.gz
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[SelectionDAG] Teach GetDemandedBits to look at the known zeros of the LHS when handling ISD::AND
If the LHS has known zeros, then the RHS immediate mask might have been simplified to remove those bits. This patch adds a call to computeKnownBits to get the known zeroes to handle that possibility. I left an early out to skip the call if all of the demanded bits are set in the mask. Differential Revision: https://reviews.llvm.org/D58464 llvm-svn: 354514
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp10
1 files changed, 7 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 65b738151e6..dd284430645 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2102,9 +2102,13 @@ SDValue SelectionDAG::GetDemandedBits(SDValue V, const APInt &Mask) {
break;
case ISD::AND: {
// X & -1 -> X (ignoring bits which aren't demanded).
- ConstantSDNode *AndVal = isConstOrConstSplat(V.getOperand(1));
- if (AndVal && Mask.isSubsetOf(AndVal->getAPIntValue()))
- return V.getOperand(0);
+ // Also handle the case where masked out bits in X are known to be zero.
+ if (ConstantSDNode *RHSC = isConstOrConstSplat(V.getOperand(1))) {
+ const APInt &AndVal = RHSC->getAPIntValue();
+ if (Mask.isSubsetOf(AndVal) ||
+ Mask.isSubsetOf(computeKnownBits(V.getOperand(0)).Zero | AndVal))
+ return V.getOperand(0);
+ }
break;
}
case ISD::ANY_EXTEND: {
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