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author | David Majnemer <david.majnemer@gmail.com> | 2015-12-12 05:38:55 +0000 |
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committer | David Majnemer <david.majnemer@gmail.com> | 2015-12-12 05:38:55 +0000 |
commit | 8a1c45d6e86d54c40835fa8638d1fd900071783c (patch) | |
tree | e485010342db16bc7c4de112e89d5b5e23b29bba /llvm/lib/CodeGen/SelectionDAG | |
parent | a38312a9a4eeb8ab8976adf5712fadd68dd763cf (diff) | |
download | bcm5719-llvm-8a1c45d6e86d54c40835fa8638d1fd900071783c.tar.gz bcm5719-llvm-8a1c45d6e86d54c40835fa8638d1fd900071783c.zip |
[IR] Reformulate LLVM's EH funclet IR
While we have successfully implemented a funclet-oriented EH scheme on
top of LLVM IR, our scheme has some notable deficiencies:
- catchendpad and cleanupendpad are necessary in the current design
but they are difficult to explain to others, even to seasoned LLVM
experts.
- catchendpad and cleanupendpad are optimization barriers. They cannot
be split and force all potentially throwing call-sites to be invokes.
This has a noticable effect on the quality of our code generation.
- catchpad, while similar in some aspects to invoke, is fairly awkward.
It is unsplittable, starts a funclet, and has control flow to other
funclets.
- The nesting relationship between funclets is currently a property of
control flow edges. Because of this, we are forced to carefully
analyze the flow graph to see if there might potentially exist illegal
nesting among funclets. While we have logic to clone funclets when
they are illegally nested, it would be nicer if we had a
representation which forbade them upfront.
Let's clean this up a bit by doing the following:
- Instead, make catchpad more like cleanuppad and landingpad: no control
flow, just a bunch of simple operands; catchpad would be splittable.
- Introduce catchswitch, a control flow instruction designed to model
the constraints of funclet oriented EH.
- Make funclet scoping explicit by having funclet instructions consume
the token produced by the funclet which contains them.
- Remove catchendpad and cleanupendpad. Their presence can be inferred
implicitly using coloring information.
N.B. The state numbering code for the CLR has been updated but the
veracity of it's output cannot be spoken for. An expert should take a
look to make sure the results are reasonable.
Reviewers: rnk, JosephTremoulet, andrew.w.kaylor
Differential Revision: http://reviews.llvm.org/D15139
llvm-svn: 255422
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 4 | ||||
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 63 | ||||
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h | 3 |
3 files changed, 26 insertions, 44 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp index ff0ccd415db..6ae38d3258d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -225,12 +225,12 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf, MMI.setHasEHFunclets(true); MF->getFrameInfo()->setHasOpaqueSPAdjustment(true); } - if (isa<CatchEndPadInst>(I) || isa<CleanupEndPadInst>(I)) { + if (isa<CatchSwitchInst>(I)) { assert(&*BB->begin() == I && "WinEHPrepare failed to remove PHIs from imaginary BBs"); continue; } - if (isa<CatchPadInst>(I) || isa<CleanupPadInst>(I)) + if (isa<FuncletPadInst>(I)) assert(&*BB->begin() == I && "WinEHPrepare failed to demote PHIs"); } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index dc2a57a860f..506115c7856 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -1184,21 +1184,7 @@ void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) { if (IsMSVCCXX || IsCoreCLR) CatchPadMBB->setIsEHFuncletEntry(); - MachineBasicBlock *NormalDestMBB = FuncInfo.MBBMap[I.getNormalDest()]; - - // Update machine-CFG edge. - FuncInfo.MBB->addSuccessor(NormalDestMBB); - - SDValue Chain = - DAG.getNode(ISD::CATCHPAD, getCurSDLoc(), MVT::Other, getControlRoot()); - - // If this is not a fall-through branch or optimizations are switched off, - // emit the branch. - if (NormalDestMBB != NextBlock(CatchPadMBB) || - TM.getOptLevel() == CodeGenOpt::None) - Chain = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, Chain, - DAG.getBasicBlock(NormalDestMBB)); - DAG.setRoot(Chain); + DAG.setRoot(DAG.getNode(ISD::CATCHPAD, getCurSDLoc(), MVT::Other, getControlRoot())); } void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) { @@ -1234,10 +1220,6 @@ void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) { DAG.setRoot(Ret); } -void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) { - llvm_unreachable("should never codegen catchendpads"); -} - void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) { // Don't emit any special code for the cleanuppad instruction. It just marks // the start of a funclet. @@ -1248,8 +1230,8 @@ void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) { /// When an invoke or a cleanupret unwinds to the next EH pad, there are /// many places it could ultimately go. In the IR, we have a single unwind /// destination, but in the machine CFG, we enumerate all the possible blocks. -/// This function skips over imaginary basic blocks that hold catchpad, -/// terminatepad, or catchendpad instructions, and finds all the "real" machine +/// This function skips over imaginary basic blocks that hold catchswitch or +/// terminatepad instructions, and finds all the "real" machine /// basic block destinations. As those destinations may not be successors of /// EHPadBB, here we also calculate the edge probability to those destinations. /// The passed-in Prob is the edge probability to EHPadBB. @@ -1276,19 +1258,18 @@ static void findUnwindDestinations( UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob); UnwindDests.back().first->setIsEHFuncletEntry(); break; - } else if (const auto *CPI = dyn_cast<CatchPadInst>(Pad)) { - // Add the catchpad handler to the possible destinations. - UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob); - // In MSVC C++, catchblocks are funclets and need prologues. - if (IsMSVCCXX || IsCoreCLR) - UnwindDests.back().first->setIsEHFuncletEntry(); - NewEHPadBB = CPI->getUnwindDest(); - } else if (const auto *CEPI = dyn_cast<CatchEndPadInst>(Pad)) - NewEHPadBB = CEPI->getUnwindDest(); - else if (const auto *CEPI = dyn_cast<CleanupEndPadInst>(Pad)) - NewEHPadBB = CEPI->getUnwindDest(); - else + } else if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) { + // Add the catchpad handlers to the possible destinations. + for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) { + UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob); + // For MSVC++ and the CLR, catchblocks are funclets and need prologues. + if (IsMSVCCXX || IsCoreCLR) + UnwindDests.back().first->setIsEHFuncletEntry(); + } + NewEHPadBB = CatchSwitch->getUnwindDest(); + } else { continue; + } BranchProbabilityInfo *BPI = FuncInfo.BPI; if (BPI && NewEHPadBB) @@ -1319,14 +1300,14 @@ void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) { DAG.setRoot(Ret); } -void SelectionDAGBuilder::visitCleanupEndPad(const CleanupEndPadInst &I) { - report_fatal_error("visitCleanupEndPad not yet implemented!"); -} - void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) { report_fatal_error("visitTerminatePad not yet implemented!"); } +void SelectionDAGBuilder::visitCatchSwitch(const CatchSwitchInst &CSI) { + report_fatal_error("visitCatchSwitch not yet implemented!"); +} + void SelectionDAGBuilder::visitRet(const ReturnInst &I) { const TargetLowering &TLI = DAG.getTargetLoweringInfo(); auto &DL = DAG.getDataLayout(); @@ -2124,8 +2105,8 @@ void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { MachineBasicBlock *InvokeMBB = FuncInfo.MBB; - // Retrieve successors. Look through artificial IR level blocks like catchpads - // and catchendpads for successors. + // Retrieve successors. Look through artificial IR level blocks like + // catchswitch for successors. MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; const BasicBlock *EHPadBB = I.getSuccessor(1); @@ -5367,8 +5348,10 @@ SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI, // Inform MachineModuleInfo of range. if (MMI.hasEHFunclets()) { + assert(CLI.CS); WinEHFuncInfo *EHInfo = DAG.getMachineFunction().getWinEHFuncInfo(); - EHInfo->addIPToStateRange(EHPadBB, BeginLabel, EndLabel); + EHInfo->addIPToStateRange(cast<InvokeInst>(CLI.CS->getInstruction()), + BeginLabel, EndLabel); } else { MMI.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel); } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h index 1171f0aad00..4f8e8132c4a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h @@ -736,9 +736,8 @@ private: void visitSwitch(const SwitchInst &I); void visitIndirectBr(const IndirectBrInst &I); void visitUnreachable(const UnreachableInst &I); - void visitCleanupEndPad(const CleanupEndPadInst &I); void visitCleanupRet(const CleanupReturnInst &I); - void visitCatchEndPad(const CatchEndPadInst &I); + void visitCatchSwitch(const CatchSwitchInst &I); void visitCatchRet(const CatchReturnInst &I); void visitCatchPad(const CatchPadInst &I); void visitTerminatePad(const TerminatePadInst &TPI); |