diff options
author | Sanjay Patel <spatel@rotateright.com> | 2016-10-11 17:05:52 +0000 |
---|---|---|
committer | Sanjay Patel <spatel@rotateright.com> | 2016-10-11 17:05:52 +0000 |
commit | 8253e15ef3555cac0bde3e1c3aa15d94da081e0b (patch) | |
tree | b19cf470f52f2552d66f85732e08235e977feb66 /llvm/lib/CodeGen/SelectionDAG | |
parent | 0354a6888fd5e189a9c17442722e65dd5a78382e (diff) | |
download | bcm5719-llvm-8253e15ef3555cac0bde3e1c3aa15d94da081e0b.tar.gz bcm5719-llvm-8253e15ef3555cac0bde3e1c3aa15d94da081e0b.zip |
[DAG] add fold for masked negated sign-extended bool
This enhances the fold added with:
https://reviews.llvm.org/rL283900
llvm-svn: 283905
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 7118b4cbf0e..b8dad384f6c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3314,18 +3314,24 @@ SDValue DAGCombiner::visitAND(SDNode *N) { if (SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N)) return Tmp; - // Masking the negated extension of a boolean is just the extended boolean: + // Masking the negated extension of a boolean is just the zero-extended + // boolean: // and (sub 0, zext(bool X)), 1 --> zext(bool X) + // and (sub 0, sext(bool X)), 1 --> zext(bool X) // // Note: the SimplifyDemandedBits fold below can make an information-losing // transform, and then we have no way to find this better fold. if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) { ConstantSDNode *SubLHS = isConstOrConstSplat(N0.getOperand(0)); SDValue SubRHS = N0.getOperand(1); - if (SubLHS && SubLHS->isNullValue() && - SubRHS.getOpcode() == ISD::ZERO_EXTEND && - SubRHS.getOperand(0).getScalarValueSizeInBits() == 1) - return SubRHS; + if (SubLHS && SubLHS->isNullValue()) { + if (SubRHS.getOpcode() == ISD::ZERO_EXTEND && + SubRHS.getOperand(0).getScalarValueSizeInBits() == 1) + return SubRHS; + if (SubRHS.getOpcode() == ISD::SIGN_EXTEND && + SubRHS.getOperand(0).getScalarValueSizeInBits() == 1) + return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, SubRHS.getOperand(0)); + } } // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) |