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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-20 21:39:52 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-20 21:39:52 +0000 |
| commit | 7d33c5739f7e287d841d2238642bfe0e913093bd (patch) | |
| tree | 7c49d9da7fbad3c1458cf805dc058f6dc565a408 /llvm/lib/CodeGen/SelectionDAG | |
| parent | f1150d3a16f9cedea0cdba10e588a91fff840223 (diff) | |
| download | bcm5719-llvm-7d33c5739f7e287d841d2238642bfe0e913093bd.tar.gz bcm5719-llvm-7d33c5739f7e287d841d2238642bfe0e913093bd.zip | |
Don't add CFG edges for redundant conditional branches.
IR that hasn't been through SimplifyCFG can look like this:
br i1 %b, label %r, label %r
Make sure we don't create duplicate Machine CFG edges in this case.
Fix the machine code verifier to accept conditional branches with a
single CFG edge.
llvm-svn: 162230
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index ae2b32969a7..f3cf7582be3 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -1601,7 +1601,10 @@ void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, // Update successor info addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); - addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); + // TrueBB and FalseBB are always different unless the incoming IR is + // degenerate. This only happens when running llc on weird IR. + if (CB.TrueBB != CB.FalseBB) + addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); // Set NextBlock to be the MBB immediately after the current one, if any. // This is used to avoid emitting unnecessary branches to the next block. |
