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| author | Richard Relph <Richard.Relph@amd.com> | 2013-03-12 18:17:18 +0000 |
|---|---|---|
| committer | Richard Relph <Richard.Relph@amd.com> | 2013-03-12 18:17:18 +0000 |
| commit | 61046a97277fead81c3d57e24cbc842763cd7c8f (patch) | |
| tree | afa93cedc40d1a71283f920b1467d21cffd6eb85 /llvm/lib/CodeGen/SelectionDAG | |
| parent | f536c6af39e59acc68cda882cc97507b1face283 (diff) | |
| download | bcm5719-llvm-61046a97277fead81c3d57e24cbc842763cd7c8f.tar.gz bcm5719-llvm-61046a97277fead81c3d57e24cbc842763cd7c8f.zip | |
Avoid generating ISD::SELECT for vector operands to SIGN_EXTEND
llvm-svn: 176881
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 716fb93b29b..61603e18f56 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4496,8 +4496,8 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { NegOne, DAG.getConstant(0, VT), cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); if (SCC.getNode()) return SCC; - if (!LegalOperations || - TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) + if (!VT.isVector() && (!LegalOperations || + TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))) return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, DAG.getSetCC(N->getDebugLoc(), TLI.getSetCCResultType(VT), |
