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author | Owen Anderson <resistor@mac.com> | 2014-01-31 00:51:43 +0000 |
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committer | Owen Anderson <resistor@mac.com> | 2014-01-31 00:51:43 +0000 |
commit | 60a4678c42d7bb4dda34b346cf580ae7abae6ac6 (patch) | |
tree | 7ddfd35cd8eb8e158e99df2505179650087b1d34 /llvm/lib/CodeGen/SelectionDAG | |
parent | 4ece7452ba9bedef856ee6df247ceee4c3101671 (diff) | |
download | bcm5719-llvm-60a4678c42d7bb4dda34b346cf580ae7abae6ac6.tar.gz bcm5719-llvm-60a4678c42d7bb4dda34b346cf580ae7abae6ac6.zip |
DAGCombine should not produce ISD::OR nodes after operation legalization if they're not legal.
llvm-svn: 200503
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index e96a7aaaf08..7dd85a8be74 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1544,8 +1544,10 @@ SDValue DAGCombiner::visitADD(SDNode *N) { // If all possibly-set bits on the LHS are clear on the RHS, return an OR. // If all possibly-set bits on the RHS are clear on the LHS, return an OR. - if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) - return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1); + if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero){ + if (!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) + return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1); + } } } |