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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-22 15:02:34 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-22 15:02:34 +0000 |
| commit | 542720b2bc48d243d2eec93157feebc37af0e202 (patch) | |
| tree | 329e82ce7ea94f5afa8290491bd0debe65636265 /llvm/lib/CodeGen/SelectionDAG | |
| parent | 1b2da771f561affe36eb5eb0c7a3d2862c5a5c1c (diff) | |
| download | bcm5719-llvm-542720b2bc48d243d2eec93157feebc37af0e202.tar.gz bcm5719-llvm-542720b2bc48d243d2eec93157feebc37af0e202.zip | |
TableGen: Support physical register inputs > 255
This was truncating register value that didn't fit in unsigned char.
Switch AMDGPU sendmsg intrinsics to using a tablegen pattern.
llvm-svn: 366695
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index bdf9f2c166e..7bef0b4ec74 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -3323,10 +3323,13 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, continue; } - case OPC_EmitCopyToReg: { + case OPC_EmitCopyToReg: + case OPC_EmitCopyToReg2: { unsigned RecNo = MatcherTable[MatcherIndex++]; assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg"); unsigned DestPhysReg = MatcherTable[MatcherIndex++]; + if (Opcode == OPC_EmitCopyToReg2) + DestPhysReg |= MatcherTable[MatcherIndex++] << 8; if (!InputChain.getNode()) InputChain = CurDAG->getEntryNode(); |
