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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-01-26 19:26:01 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-01-26 19:26:01 +0000 |
| commit | 4b4622454c2836ed27bf2fcb5ad30256fe14802e (patch) | |
| tree | 808d7fe0bf356d9ee0f6e06ff0eeba27c54fff60 /llvm/lib/CodeGen/SelectionDAG | |
| parent | 5e235d3a7e97677ef1c6df4859b2e5b60bc70201 (diff) | |
| download | bcm5719-llvm-4b4622454c2836ed27bf2fcb5ad30256fe14802e.tar.gz bcm5719-llvm-4b4622454c2836ed27bf2fcb5ad30256fe14802e.zip | |
During bittest switch lowering emit shift in the test block, which should (theoretically)
allow us to generate more efficient code. We don't do this now though :)
llvm-svn: 63027
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index f971069e82f..c467d9c3cb4 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -1416,14 +1416,8 @@ void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) { else ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); - // Make desired shift - SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), - DAG.getConstant(1, TLI.getPointerTy()), - ShiftOp); - - unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); - SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal); - B.Reg = SwitchReg; + B.Reg = FuncInfo.MakeReg(TLI.getShiftAmountTy()); + SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), B.Reg, ShiftOp); // Set NextBlock to be the MBB immediately after the current one, if any. // This is used to avoid emitting unnecessary branches to the next block. @@ -1453,10 +1447,14 @@ void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) { void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, unsigned Reg, BitTestCase &B) { - // Emit bit tests and jumps - SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg, - TLI.getPointerTy()); + // Make desired shift + SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), Reg, + TLI.getShiftAmountTy()); + SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), + DAG.getConstant(1, TLI.getPointerTy()), + ShiftOp); + // Emit bit tests and jumps SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal, DAG.getConstant(B.Mask, TLI.getPointerTy())); SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp.getValueType()), |
