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| author | Sam Parker <sam.parker@arm.com> | 2017-11-16 11:28:26 +0000 | 
|---|---|---|
| committer | Sam Parker <sam.parker@arm.com> | 2017-11-16 11:28:26 +0000 | 
| commit | 43fa5911a18811307ce080ec8dda37c3112766c6 (patch) | |
| tree | 06fdb356023695781b4981076c2c50b3f25f7826 /llvm/lib/CodeGen/SelectionDAG | |
| parent | 9844efc044126d3bf5a1bfae3f3cfb9c40a987e6 (diff) | |
| download | bcm5719-llvm-43fa5911a18811307ce080ec8dda37c3112766c6.tar.gz bcm5719-llvm-43fa5911a18811307ce080ec8dda37c3112766c6.zip | |
[DAGCombine] Enable more srl -> load combines
Change the calculation for the desired ValueType for non-sign
extending loads, as in those cases we don't care about the
higher bits. This creates a smaller ExtVT and allows for such
combinations as:
(srl (zextload i16, [addr]), 8) -> (zextload i8, [addr + 1])
Differential Revision: https://reviews.llvm.org/D40034
llvm-svn: 318390
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 21 | 
1 files changed, 16 insertions, 5 deletions
| diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index dd8d613dcf7..0d397b71d87 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -8041,13 +8041,24 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {      ExtType = ISD::SEXTLOAD;      ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();    } else if (Opc == ISD::SRL) { -    // Another special-case: SRL is basically zero-extending a narrower value. +    // Another special-case: SRL is basically zero-extending a narrower value, +    // or it maybe shifting a higher subword, half or byte into the lowest +    // bits.      ExtType = ISD::ZEXTLOAD;      N0 = SDValue(N, 0); -    ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); -    if (!N01) return SDValue(); -    ExtVT = EVT::getIntegerVT(*DAG.getContext(), -                              VT.getSizeInBits() - N01->getZExtValue()); + +    auto *LN0 = dyn_cast<LoadSDNode>(N0.getOperand(0)); +    auto *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); +    if (!N01 || !LN0) +      return SDValue(); + +    uint64_t ShiftAmt = N01->getZExtValue(); +    uint64_t MemoryWidth = LN0->getMemoryVT().getSizeInBits(); +    if (LN0->getExtensionType() != ISD::SEXTLOAD && MemoryWidth > ShiftAmt) +      ExtVT = EVT::getIntegerVT(*DAG.getContext(), MemoryWidth - ShiftAmt); +    else +      ExtVT = EVT::getIntegerVT(*DAG.getContext(), +                                VT.getSizeInBits() - ShiftAmt);    }    if (LegalOperations && !TLI.isLoadExtLegal(ExtType, VT, ExtVT))      return SDValue(); | 

