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authorSam Parker <sam.parker@arm.com>2018-01-08 13:21:24 +0000
committerSam Parker <sam.parker@arm.com>2018-01-08 13:21:24 +0000
commit3800f0f11d61968ae32ee79bfbdb0b4d808985ba (patch)
tree04f79d7c8c7d9e3426394777fb234d10afd06583 /llvm/lib/CodeGen/SelectionDAG
parent22f208f034232181be547e7d16810272004f646e (diff)
downloadbcm5719-llvm-3800f0f11d61968ae32ee79bfbdb0b4d808985ba.tar.gz
bcm5719-llvm-3800f0f11d61968ae32ee79bfbdb0b4d808985ba.zip
[DAGCombine] Fix for PR35761
I had falsely assumed that constant operands would be operand(1) of the bin ops that may need their constant operand to be masked. Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=35761 Differential Revision: https://reviews.llvm.org/D41667 llvm-svn: 321991
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp14
1 files changed, 10 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 1fcb010eac5..d823c455b5e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3923,10 +3923,16 @@ bool DAGCombiner::BackwardsPropagateMask(SDNode *N, SelectionDAG &DAG) {
// Narrow any constants that need it.
for (auto *LogicN : NodesWithConsts) {
- auto *C = cast<ConstantSDNode>(LogicN->getOperand(1));
- SDValue And = DAG.getNode(ISD::AND, SDLoc(C), C->getValueType(0),
- SDValue(C, 0), MaskOp);
- DAG.UpdateNodeOperands(LogicN, LogicN->getOperand(0), And);
+ SDValue Op0 = LogicN->getOperand(0);
+ SDValue Op1 = LogicN->getOperand(1);
+
+ if (isa<ConstantSDNode>(Op0))
+ std::swap(Op0, Op1);
+
+ SDValue And = DAG.getNode(ISD::AND, SDLoc(Op1), Op1.getValueType(),
+ Op1, MaskOp);
+
+ DAG.UpdateNodeOperands(LogicN, Op0, And);
}
// Create narrow loads.
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