Add support for putting NamedRegionTimers in TimerGroups, and

use a timer group for the timers in SelectionDAGISel. Also,
Split scheduling out from emitting, to give each their own
timer.

llvm-svn: 53476

3 files changed, 33 insertions, 22 deletions

diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
index 8a1dade30b3..50331788ec1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
@@ -103,9 +103,6 @@ void ScheduleDAGList::Schedule() {
   DOUT << "*** Final schedule ***\n";
   DEBUG(dumpSchedule());
   DOUT << "\n";
-  
-  // Emit in scheduled order
-  EmitSchedule();
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 287e8c5b0e5..ea4cc65bea8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -208,9 +208,6 @@ void ScheduleDAGRRList::Schedule() {
   DOUT << "*** Final schedule ***\n";
   DEBUG(dumpSchedule());
   DOUT << "\n";
-  
-  // Emit in scheduled order
-  EmitSchedule();
 }
 
 /// CommuteNodesToReducePressure - If a node is two-address and commutable, and
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index b4b81cd4f13..e9bac8a930d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -5284,10 +5284,11 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) {
 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
   DOUT << "Lowered selection DAG:\n";
   DEBUG(DAG.dump());
+  std::string GroupName = "Instruction Selection and Scheduling";
 
   // Run the DAG combiner in pre-legalize mode.
   if (TimePassesIsEnabled) {
-    NamedRegionTimer T("DAG Combining 1");
+    NamedRegionTimer T("DAG Combining 1", GroupName);
     DAG.Combine(false, *AA);
   } else {
     DAG.Combine(false, *AA);
@@ -5304,7 +5305,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
   }
   
   if (TimePassesIsEnabled) {
-    NamedRegionTimer T("DAG Legalization");
+    NamedRegionTimer T("DAG Legalization", GroupName);
     DAG.Legalize();
   } else {
     DAG.Legalize();
@@ -5315,7 +5316,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
   
   // Run the DAG combiner in post-legalize mode.
   if (TimePassesIsEnabled) {
-    NamedRegionTimer T("DAG Combining 2");
+    NamedRegionTimer T("DAG Combining 2", GroupName);
     DAG.Combine(true, *AA);
   } else {
     DAG.Combine(true, *AA);
@@ -5332,24 +5333,41 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
   // Third, instruction select all of the operations to machine code, adding the
   // code to the MachineBasicBlock.
   if (TimePassesIsEnabled) {
-    NamedRegionTimer T("Instruction Selection");
+    NamedRegionTimer T("Instruction Selection", GroupName);
     InstructionSelect(DAG);
   } else {
     InstructionSelect(DAG);
   }
 
+  // Schedule machine code.
+  ScheduleDAG *Scheduler;
+  if (TimePassesIsEnabled) {
+    NamedRegionTimer T("Instruction Scheduling", GroupName);
+    Scheduler = Schedule(DAG);
+  } else {
+    Scheduler = Schedule(DAG);
+  }
+
   // Emit machine code to BB.  This can change 'BB' to the last block being 
   // inserted into.
   if (TimePassesIsEnabled) {
-    NamedRegionTimer T("Instruction Scheduling");
-    ScheduleAndEmitDAG(DAG);
+    NamedRegionTimer T("Instruction Creation", GroupName);
+    Scheduler->EmitSchedule();
   } else {
-    ScheduleAndEmitDAG(DAG);
+    Scheduler->EmitSchedule();
+  }
+
+  // Free the scheduler state.
+  if (TimePassesIsEnabled) {
+    NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
+    delete Scheduler;
+  } else {
+    delete Scheduler;
   }
 
   // Perform target specific isel post processing.
   if (TimePassesIsEnabled) {
-    NamedRegionTimer T("Instruction Selection Post Processing");
+    NamedRegionTimer T("Instruction Selection Post Processing", GroupName);
     InstructionSelectPostProcessing(DAG);
   } else {
     InstructionSelectPostProcessing(DAG);
@@ -5597,10 +5615,10 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
 }
 
 
-//===----------------------------------------------------------------------===//
-/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
+/// Schedule - Pick a safe ordering for instructions for each
 /// target node in the graph.
-void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
+///
+ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
   if (ViewSchedDAGs) DAG.viewGraph();
 
   RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
@@ -5610,12 +5628,11 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
     RegisterScheduler::setDefault(Ctor);
   }
   
-  ScheduleDAG *SL = Ctor(this, &DAG, BB, FastISel);
-  BB = SL->Run();
-
-  if (ViewSUnitDAGs) SL->viewGraph();
+  ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel);
+  BB = Scheduler->Run();
 
-  delete SL;
+  if (ViewSUnitDAGs) Scheduler->viewGraph();
+  return Scheduler;
 }