Skeleton of the list schedule.

llvm-svn: 25544

2 files changed, 65 insertions, 0 deletions

diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
new file mode 100644
index 00000000000..dca430257cb
--- /dev/null
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
@@ -0,0 +1,61 @@
+//===-- ScheduleDAGSimple.cpp - Implement a list scheduler for isel DAG ---===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by Evan Cheng and is distributed under the
+// University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This implements a simple two pass scheduler.  The first pass attempts to push
+// backward any lengthy instructions and critical paths.  The second pass packs
+// instructions into semi-optimal time slots.
+//
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "sched"
+#include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include <algorithm>
+#include <queue>
+using namespace llvm;
+
+
+namespace llvm {
+/// Sorting functions for ready queue.
+struct LSSortPred : public std::binary_function<SDOperand, SDOperand, bool> {
+  bool operator()(const SDOperand* left, const SDOperand* right) const {
+    return true;
+  }
+};
+
+/// ScheduleDAGList - List scheduler.
+
+class ScheduleDAGList : public ScheduleDAG {
+private:
+  LSSortPred &Cmp;
+
+  // Ready queue
+  std::priority_queue<SDOperand*, std::vector<SDOperand*>, LSSortPred> Ready;
+                      
+public:
+  ScheduleDAGList(SelectionDAG &dag, MachineBasicBlock *bb,
+                  const TargetMachine &tm, LSSortPred cmp)
+    : ScheduleDAG(listSchedulingBURR, dag, bb, tm), Cmp(cmp), Ready(Cmp)
+  {};
+
+  void Schedule();
+};
+}  // end namespace llvm
+
+void ScheduleDAGList::Schedule() {
+}
+  
+
+llvm::ScheduleDAG*
+llvm::createBURRListDAGScheduler(SelectionDAG &DAG,
+                                 MachineBasicBlock *BB) {
+  return new ScheduleDAGList(DAG, BB, DAG.getTarget(), LSSortPred());
+}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index aa410bd0a6b..6cc4d436e90 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -69,6 +69,8 @@ namespace {
       clEnumValN(simpleNoItinScheduling, "simple-noitin",
                  "Simple two pass scheduling: Same as simple "
                  "except using generic latency"),
+      clEnumValN(listSchedulingBURR, "list-BURR",
+                 "Bottom up register reduction list scheduling"),
       clEnumValEnd));
 } // namespace
 
@@ -1775,6 +1777,8 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
   case simpleNoItinScheduling:
     SL = createSimpleDAGScheduler(ISHeuristic, DAG, BB);
     break;
+  case listSchedulingBURR:
+    SL = createBURRListDAGScheduler(DAG, BB);
   }
   BB = SL->Run();
 }