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authorChris Lattner <sabre@nondot.org>2006-10-12 20:23:19 +0000
committerChris Lattner <sabre@nondot.org>2006-10-12 20:23:19 +0000
commit2e33fb453bd4330285007a22ae53e8b3521aba6a (patch)
tree3b1925225a0c698a6f149bf594e89e96e174f65f /llvm/lib/CodeGen/SelectionDAG
parenta7956d2894cedf46fd3b36e8d0301588edad11c8 (diff)
downloadbcm5719-llvm-2e33fb453bd4330285007a22ae53e8b3521aba6a.tar.gz
bcm5719-llvm-2e33fb453bd4330285007a22ae53e8b3521aba6a.zip
add a minor dag combine noticed when looking at PR945
llvm-svn: 30915
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp7
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 2c15f39db4a..70ff8371f79 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1664,6 +1664,13 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) {
return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
}
+ // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
+ // bit, which is unmodified by sra.
+ if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
+ if (N0.getOpcode() == ISD::SRA)
+ return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
+ }
+
// fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
if (N1C && N0.getOpcode() == ISD::CTLZ &&
N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
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