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author | Nadav Rotem <nadav.rotem@intel.com> | 2012-01-03 22:12:28 +0000 |
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committer | Nadav Rotem <nadav.rotem@intel.com> | 2012-01-03 22:12:28 +0000 |
commit | 1e7dda13c822c330759baf6950fef2ec22f99ee6 (patch) | |
tree | 61b8821fc09bba56a951b54bb945cae5c37327ad /llvm/lib/CodeGen/SelectionDAG | |
parent | 950e534e606c38798220a419c5be0d9470914e33 (diff) | |
download | bcm5719-llvm-1e7dda13c822c330759baf6950fef2ec22f99ee6.tar.gz bcm5719-llvm-1e7dda13c822c330759baf6950fef2ec22f99ee6.zip |
Fix incorrect widening of the bitcast sdnode in case the incoming operand is integer-promoted.
llvm-svn: 147484
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 7ca0d1e5c0f..6b267c311d8 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -1571,6 +1571,12 @@ SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) { case TargetLowering::TypeLegal: break; case TargetLowering::TypePromoteInteger: + // If the incoming type is a vector that is being promoted, then + // we know that the elements are arranged differently and that we + // must perform the conversion using a stack slot. + if (InVT.isVector()) + break; + // If the InOp is promoted to the same size, convert it. Otherwise, // fall out of the switch and widen the promoted input. InOp = GetPromotedInteger(InOp); |