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| author | Hal Finkel <hfinkel@anl.gov> | 2015-04-22 11:32:25 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2015-04-22 11:32:25 +0000 |
| commit | 0d49cf2645289cfad9a99b7c2e19cf7645770428 (patch) | |
| tree | 250778a7f6b08f94475641abbc17eff0bac8c8f4 /llvm/lib/CodeGen/SelectionDAG | |
| parent | 98eb6e3d41afa29e490d06b15de1213bf5a6947c (diff) | |
| download | bcm5719-llvm-0d49cf2645289cfad9a99b7c2e19cf7645770428.tar.gz bcm5719-llvm-0d49cf2645289cfad9a99b7c2e19cf7645770428.zip | |
[DAGCombine] Disable select(c, load,load) for indexed loads
This turned up after r235333, but was a pre-existing bug. The optimization
which transforms select(c, load, load) into a load of a select of the addresses
does not handle indexed loads (pre/post inc/dec). However, it did not check for
them either, leading to a crash if it tried to transform one of them.
llvm-svn: 235497
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 1179b7617e6..4b98da70720 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -12799,6 +12799,9 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, if (LHS.getOperand(0) != RHS.getOperand(0) || // Do not let this transformation reduce the number of volatile loads. LLD->isVolatile() || RLD->isVolatile() || + // FIXME: If either is a pre/post inc/dec load, + // we'd need to split out the address adjustment. + LLD->isIndexed() || RLD->isIndexed() || // If this is an EXTLOAD, the VT's must match. LLD->getMemoryVT() != RLD->getMemoryVT() || // If this is an EXTLOAD, the kind of extension must match. |
