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| author | Duncan Sands <baldrick@free.fr> | 2008-06-17 03:24:13 +0000 |
|---|---|---|
| committer | Duncan Sands <baldrick@free.fr> | 2008-06-17 03:24:13 +0000 |
| commit | 0ae829e5d14d368d0e43ba74e0f39925da8c1788 (patch) | |
| tree | d4cc0fe5b2b6caa5607488318b7660160d49fc6e /llvm/lib/CodeGen/SelectionDAG | |
| parent | c6501dbc10ea73a6986efc2226fe68be59ba922e (diff) | |
| download | bcm5719-llvm-0ae829e5d14d368d0e43ba74e0f39925da8c1788.tar.gz bcm5719-llvm-0ae829e5d14d368d0e43ba74e0f39925da8c1788.zip | |
Fix spelling.
llvm-svn: 52381
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index a55f904b218..50799d10edc 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -4283,7 +4283,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { // Copy the output from the appropriate register. Find a register that // we can use. if (OpInfo.AssignedRegs.Regs.empty()) { - cerr << "Couldn't allocate output reg for contraint '" + cerr << "Couldn't allocate output reg for constraint '" << OpInfo.ConstraintCode << "'!\n"; exit(1); } |
